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author | Mon P Wang <wangmp@apple.com> | 2008-12-15 21:44:00 +0000 |
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committer | Mon P Wang <wangmp@apple.com> | 2008-12-15 21:44:00 +0000 |
commit | 93b3b928d70df956b81ab1bffb7e8bab4b0c8fd7 (patch) | |
tree | 4a0953429cc8a2c04d8d9cdf5f06f590a59c32ae /lib | |
parent | 344b41cfbd30980a2194c56db382b0537d087ea9 (diff) | |
download | external_llvm-93b3b928d70df956b81ab1bffb7e8bab4b0c8fd7.zip external_llvm-93b3b928d70df956b81ab1bffb7e8bab4b0c8fd7.tar.gz external_llvm-93b3b928d70df956b81ab1bffb7e8bab4b0c8fd7.tar.bz2 |
Added support for splitting and scalarizing vector shifts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61050 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeTypes.h | 1 | ||||
-rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 18 |
2 files changed, 19 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/lib/CodeGen/SelectionDAG/LegalizeTypes.h index 36c89ad..9a42c56 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeTypes.h +++ b/lib/CodeGen/SelectionDAG/LegalizeTypes.h @@ -496,6 +496,7 @@ private: // Vector Result Scalarization: <1 x ty> -> ty. void ScalarizeVectorResult(SDNode *N, unsigned OpNo); SDValue ScalarizeVecRes_BinOp(SDNode *N); + SDValue ScalarizeVecRes_ShiftOp(SDNode *N); SDValue ScalarizeVecRes_UnaryOp(SDNode *N); SDValue ScalarizeVecRes_BIT_CONVERT(SDNode *N); diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index 35eb7cd..5f15fa5 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -91,6 +91,10 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) { case ISD::UDIV: case ISD::UREM: case ISD::XOR: R = ScalarizeVecRes_BinOp(N); break; + + case ISD::SHL: + case ISD::SRA: + case ISD::SRL: R = ScalarizeVecRes_ShiftOp(N); break; } // If R is null, the sub-method took care of registering the result. @@ -104,6 +108,17 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) { return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS); } +SDValue DAGTypeLegalizer::ScalarizeVecRes_ShiftOp(SDNode *N) { + SDValue LHS = GetScalarizedVector(N->getOperand(0)); + SDValue ShiftAmt = GetScalarizedVector(N->getOperand(1)); + if (TLI.getShiftAmountTy().bitsLT(ShiftAmt.getValueType())) + ShiftAmt = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), ShiftAmt); + else if (TLI.getShiftAmountTy().bitsGT(ShiftAmt.getValueType())) + ShiftAmt = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), ShiftAmt); + + return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, ShiftAmt); +} + SDValue DAGTypeLegalizer::ScalarizeVecRes_BIT_CONVERT(SDNode *N) { MVT NewVT = N->getValueType(0).getVectorElementType(); return DAG.getNode(ISD::BIT_CONVERT, NewVT, N->getOperand(0)); @@ -392,6 +407,9 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) { case ISD::AND: case ISD::OR: case ISD::XOR: + case ISD::SHL: + case ISD::SRA: + case ISD::SRL: case ISD::UREM: case ISD::SREM: case ISD::FREM: SplitVecRes_BinOp(N, Lo, Hi); break; |