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| author | Dan Gohman <gohman@apple.com> | 2008-05-12 20:22:45 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2008-05-12 20:22:45 +0000 |
| commit | 9499b7186b96cb4cb7614e35f8f397c52f207469 (patch) | |
| tree | 2ec4ccd26ff5fe8d50dae45fac3947eaad1b9612 /lib | |
| parent | 51d2ed179b34646f3e02da59fe100dd595c365b3 (diff) | |
| download | external_llvm-9499b7186b96cb4cb7614e35f8f397c52f207469.zip external_llvm-9499b7186b96cb4cb7614e35f8f397c52f207469.tar.gz external_llvm-9499b7186b96cb4cb7614e35f8f397c52f207469.tar.bz2 | |
Fix a copy+paste bug; pseudo-instructions shouldn't have
encoding information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50997 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/X86/X86InstrInfo.td | 35 |
1 files changed, 14 insertions, 21 deletions
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index af61540..6b0a19b 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -2601,58 +2601,51 @@ def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val), // Atomic exchange and and, or, xor let Constraints = "$val = $dst", Defs = [EFLAGS], usesCustomDAGSchedInserter = 1 in { -def ATOMAND32 : I<0xC1, MRMSrcMem,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), +def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), "#ATOMAND32 PSUEDO!", - [(set GR32:$dst, (atomic_load_and addr:$ptr, GR32:$val))]>, - TB, LOCK; + [(set GR32:$dst, (atomic_load_and addr:$ptr, GR32:$val))]>; } let Constraints = "$val = $dst", Defs = [EFLAGS], usesCustomDAGSchedInserter = 1 in { -def ATOMOR32 : I<0xC1, MRMSrcMem, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), +def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), "#ATOMOR32 PSUEDO!", - [(set GR32:$dst, (atomic_load_or addr:$ptr, GR32:$val))]>, - TB, LOCK; + [(set GR32:$dst, (atomic_load_or addr:$ptr, GR32:$val))]>; } let Constraints = "$val = $dst", Defs = [EFLAGS], usesCustomDAGSchedInserter = 1 in { -def ATOMXOR32 : I<0xC1, MRMSrcMem,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), +def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), "#ATOMXOR32 PSUEDO!", - [(set GR32:$dst, (atomic_load_xor addr:$ptr, GR32:$val))]>, - TB, LOCK; + [(set GR32:$dst, (atomic_load_xor addr:$ptr, GR32:$val))]>; } let Constraints = "$val = $dst", Defs = [EFLAGS], usesCustomDAGSchedInserter = 1 in { -def ATOMMIN32: I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val), +def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val), "#ATOMMIN32 PSUEDO!", - [(set GR32:$dst, (atomic_load_min addr:$ptr, GR32:$val))]>, - TB, LOCK; + [(set GR32:$dst, (atomic_load_min addr:$ptr, GR32:$val))]>; } let Constraints = "$val = $dst", Defs = [EFLAGS], usesCustomDAGSchedInserter = 1 in { -def ATOMMAX32: I<0xC1, MRMSrcMem, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), +def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), "#ATOMMAX32 PSUEDO!", - [(set GR32:$dst, (atomic_load_max addr:$ptr, GR32:$val))]>, - TB, LOCK; + [(set GR32:$dst, (atomic_load_max addr:$ptr, GR32:$val))]>; } let Constraints = "$val = $dst", Defs = [EFLAGS], usesCustomDAGSchedInserter = 1 in { -def ATOMUMIN32: I<0xC1, MRMSrcMem,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), +def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), "#ATOMUMIN32 PSUEDO!", - [(set GR32:$dst, (atomic_load_umin addr:$ptr, GR32:$val))]>, - TB, LOCK; + [(set GR32:$dst, (atomic_load_umin addr:$ptr, GR32:$val))]>; } let Constraints = "$val = $dst", Defs = [EFLAGS], usesCustomDAGSchedInserter = 1 in { -def ATOMUMAX32: I<0xC1, MRMSrcMem,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), +def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), "#ATOMUMAX32 PSUEDO!", - [(set GR32:$dst, (atomic_load_umax addr:$ptr, GR32:$val))]>, - TB, LOCK; + [(set GR32:$dst, (atomic_load_umax addr:$ptr, GR32:$val))]>; } //===----------------------------------------------------------------------===// |