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author | Evan Cheng <evan.cheng@apple.com> | 2006-08-26 05:34:46 +0000 |
---|---|---|
committer | Evan Cheng <evan.cheng@apple.com> | 2006-08-26 05:34:46 +0000 |
commit | 9ade218533429146731213eacb7e12060e65ff58 (patch) | |
tree | 6897f73aa4ad96f2595491af9bdd22b503d83e53 /lib | |
parent | 2a318cfad5c1be3d28b48076e991baffa30aa9b5 (diff) | |
download | external_llvm-9ade218533429146731213eacb7e12060e65ff58.zip external_llvm-9ade218533429146731213eacb7e12060e65ff58.tar.gz external_llvm-9ade218533429146731213eacb7e12060e65ff58.tar.bz2 |
Select() no longer require Result operand by reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29898 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/Target/ARM/ARMISelDAGToDAG.cpp | 6 | ||||
-rw-r--r-- | lib/Target/Alpha/AlphaISelDAGToDAG.cpp | 50 | ||||
-rw-r--r-- | lib/Target/IA64/IA64ISelDAGToDAG.cpp | 33 | ||||
-rw-r--r-- | lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 18 | ||||
-rw-r--r-- | lib/Target/Sparc/SparcISelDAGToDAG.cpp | 10 | ||||
-rw-r--r-- | lib/Target/X86/X86ISelDAGToDAG.cpp | 33 |
6 files changed, 68 insertions, 82 deletions
diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp index 33a068d..9dd1461 100644 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -430,7 +430,7 @@ public: : SelectionDAGISel(Lowering), Lowering(TM) { } - SDNode *Select(SDOperand &Result, SDOperand Op); + SDNode *Select(SDOperand Op); virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); bool SelectAddrRegImm(SDOperand N, SDOperand &Offset, SDOperand &Base); @@ -496,12 +496,12 @@ bool ARMDAGToDAGISel::SelectAddrRegImm(SDOperand N, SDOperand &Offset, return true; //any address fits in a register } -SDNode *ARMDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { +SDNode *ARMDAGToDAGISel::Select(SDOperand Op) { SDNode *N = Op.Val; switch (N->getOpcode()) { default: - return SelectCode(Result, Op); + return SelectCode(Op); break; } return NULL; diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp index 2fb8a22..d84f260 100644 --- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp +++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp @@ -110,7 +110,7 @@ namespace { // Select - Convert the specified operand from a target-independent to a // target-specific node if it hasn't already been changed. - SDNode *Select(SDOperand &Result, SDOperand Op); + SDNode *Select(SDOperand Op); /// InstructionSelectBasicBlock - This callback is invoked by /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. @@ -145,7 +145,7 @@ namespace { private: SDOperand getGlobalBaseReg(); SDOperand getGlobalRetAddr(); - SDOperand SelectCALL(SDOperand Op); + void SelectCALL(SDOperand Op); }; } @@ -182,18 +182,17 @@ void AlphaDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { // Select - Convert the specified operand from a target-independent to a // target-specific node if it hasn't already been changed. -SDNode *AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { +SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) { SDNode *N = Op.Val; if (N->getOpcode() >= ISD::BUILTIN_OP_END && N->getOpcode() < AlphaISD::FIRST_NUMBER) { - Result = Op; return NULL; // Already selected. } switch (N->getOpcode()) { default: break; case AlphaISD::CALL: - Result = SelectCALL(Op); + SelectCALL(Op); return NULL; case ISD::FrameIndex: { @@ -202,14 +201,16 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { CurDAG->getTargetFrameIndex(FI, MVT::i32), getI64Imm(0)).Val; } - case AlphaISD::GlobalBaseReg: - Result = getGlobalBaseReg(); + case AlphaISD::GlobalBaseReg: { + SDOperand Result = getGlobalBaseReg(); ReplaceUses(Op, Result); return NULL; - case AlphaISD::GlobalRetAddr: - Result = getGlobalRetAddr(); + } + case AlphaISD::GlobalRetAddr: { + SDOperand Result = getGlobalRetAddr(); ReplaceUses(Op, Result); return NULL; + } case AlphaISD::DivCall: { SDOperand Chain = CurDAG->getEntryNode(); @@ -236,17 +237,16 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { case ISD::READCYCLECOUNTER: { SDOperand Chain = N->getOperand(0); AddToISelQueue(Chain); //Select chain - Result = SDOperand(CurDAG->getTargetNode(Alpha::RPCC, MVT::i64, MVT::Other, - Chain), Op.ResNo); - return Result.Val; + return CurDAG->getTargetNode(Alpha::RPCC, MVT::i64, MVT::Other, + Chain); } case ISD::Constant: { uint64_t uval = cast<ConstantSDNode>(N)->getValue(); if (uval == 0) { - Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), Alpha::R31, - MVT::i64); + SDOperand Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), + Alpha::R31, MVT::i64); ReplaceUses(Op, Result); return NULL; } @@ -329,10 +329,9 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { CurDAG->getRegister(Alpha::R31, MVT::i64), ST), 0); } - Result = SDOperand(CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64, - CurDAG->getRegister(Alpha::R31, MVT::i64), - LD), 0); - return Result.Val; + return CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64, + CurDAG->getRegister(Alpha::R31, MVT::i64), + LD); } break; @@ -366,9 +365,8 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { CurDAG->getRegister(Alpha::R31, MVT::i64), ST), 0); } - Result = SDOperand(CurDAG->getTargetNode(isDouble?Alpha::FCMOVNET:Alpha::FCMOVNES, - MVT::f64, FV, TV, LD), 0); - return Result.Val; + return CurDAG->getTargetNode(isDouble?Alpha::FCMOVNET:Alpha::FCMOVNES, + MVT::f64, FV, TV, LD); } break; @@ -397,9 +395,8 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { SDOperand(CurDAG->getTargetNode(Alpha::ZAPNOTi, MVT::i64, N->getOperand(0).getOperand(0), getI64Imm(get_zapImm(mask))), 0); - Result = SDOperand(CurDAG->getTargetNode(Alpha::SRL, MVT::i64, Z, - getI64Imm(sval)), 0); - return Result.Val; + return CurDAG->getTargetNode(Alpha::SRL, MVT::i64, Z, + getI64Imm(sval)); } } break; @@ -407,10 +404,10 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { } - return SelectCode(Result, Op); + return SelectCode(Op); } -SDOperand AlphaDAGToDAGISel::SelectCALL(SDOperand Op) { +void AlphaDAGToDAGISel::SelectCALL(SDOperand Op) { //TODO: add flag stuff to prevent nondeturministic breakage! SDNode *N = Op.Val; @@ -500,7 +497,6 @@ SDOperand AlphaDAGToDAGISel::SelectCALL(SDOperand Op) { CallResults.push_back(Chain); for (unsigned i = 0, e = CallResults.size(); i != e; ++i) ReplaceUses(Op.getValue(i), CallResults[i]); - return CallResults[Op.ResNo]; } diff --git a/lib/Target/IA64/IA64ISelDAGToDAG.cpp b/lib/Target/IA64/IA64ISelDAGToDAG.cpp index f61c9e1..b384705 100644 --- a/lib/Target/IA64/IA64ISelDAGToDAG.cpp +++ b/lib/Target/IA64/IA64ISelDAGToDAG.cpp @@ -65,7 +65,7 @@ namespace { // Select - Convert the specified operand from a target-independent to a // target-specific node if it hasn't already been changed. - SDNode *Select(SDOperand &Result, SDOperand N); + SDNode *Select(SDOperand N); SDNode *SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS, unsigned OCHi, unsigned OCLo, @@ -94,7 +94,7 @@ namespace { #include "IA64GenDAGISel.inc" private: - SDOperand SelectDIV(SDOperand Op); + SDNode *SelectDIV(SDOperand Op); }; } @@ -111,7 +111,7 @@ void IA64DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { ScheduleAndEmitDAG(DAG); } -SDOperand IA64DAGToDAGISel::SelectDIV(SDOperand Op) { +SDNode *IA64DAGToDAGISel::SelectDIV(SDOperand Op) { SDNode *N = Op.Val; SDOperand Chain = N->getOperand(0); SDOperand Tmp1 = N->getOperand(0); @@ -245,7 +245,7 @@ SDOperand IA64DAGToDAGISel::SelectDIV(SDOperand Op) { Result = CurDAG->getTargetNode(IA64::TCFMADS0, MVT::f64, // d.p. s0 rndg! TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR); Chain = SDOperand(Result, 1); - return SDOperand(Result, 0); // XXX: early exit! + return Result; // XXX: early exit! } else { // this is *not* an FP divide, so there's a bit left to do: SDOperand TmpQ2, TmpR2, TmpQ3, TmpQ; @@ -292,19 +292,17 @@ SDOperand IA64DAGToDAGISel::SelectDIV(SDOperand Op) { Chain = SDOperand(Result, 1); } - return SDOperand(Result, 0); + return Result; } // wasn't an FP divide } // Select - Convert the specified operand from a target-independent to a // target-specific node if it hasn't already been changed. -SDNode *IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { +SDNode *IA64DAGToDAGISel::Select(SDOperand Op) { SDNode *N = Op.Val; if (N->getOpcode() >= ISD::BUILTIN_OP_END && - N->getOpcode() < IA64ISD::FIRST_NUMBER) { - Result = Op; + N->getOpcode() < IA64ISD::FIRST_NUMBER) return NULL; // Already selected. - } switch (N->getOpcode()) { default: break; @@ -379,15 +377,13 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { for (unsigned i = 0, e = CallResults.size(); i != e; ++i) ReplaceUses(Op.getValue(i), CallResults[i]); - Result = CallResults[Op.ResNo]; return NULL; } case IA64ISD::GETFD: { SDOperand Input = N->getOperand(0); AddToISelQueue(Input); - Result = SDOperand(CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Input), 0); - return Result.Val; + return CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Input); } case ISD::FDIV: @@ -395,8 +391,7 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { case ISD::UDIV: case ISD::SREM: case ISD::UREM: - Result = SelectDIV(Op); - return Result.Val; + return SelectDIV(Op); case ISD::TargetConstantFP: { SDOperand Chain = CurDAG->getEntryNode(); // this is a constant, so.. @@ -425,9 +420,8 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { Constant *C = CP->get(); SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64, CP->getAlignment()); - Result = SDOperand(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ? - CurDAG->getRegister(IA64::r1, MVT::i64), CPI), 0); - return Result.Val; + return CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ? + CurDAG->getRegister(IA64::r1, MVT::i64), CPI); } case ISD::GlobalAddress: { @@ -435,8 +429,7 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64); SDOperand Tmp = SDOperand(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, CurDAG->getRegister(IA64::r1, MVT::i64), GA), 0); - Result = SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp), 0); - return Result.Val; + return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp); } /* XXX case ISD::ExternalSymbol: { @@ -564,7 +557,7 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { N->getOperand(1), N0).Val; } - return SelectCode(Result, Op); + return SelectCode(Op); } diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index 40f1005..22752ab 100644 --- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -79,11 +79,11 @@ namespace { /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC /// base register. Return the virtual register that holds this value. - SDOperand getGlobalBaseReg(); + SDNode *getGlobalBaseReg(); // Select - Convert the specified operand from a target-independent to a // target-specific node if it hasn't already been changed. - SDNode *Select(SDOperand &Result, SDOperand Op); + SDNode *Select(SDOperand Op); SDNode *SelectBitfieldInsert(SDNode *N); @@ -252,7 +252,7 @@ void PPCDAGToDAGISel::InsertVRSaveCode(Function &F) { /// getGlobalBaseReg - Output the instructions required to put the /// base address to use for accessing globals into a register. /// -SDOperand PPCDAGToDAGISel::getGlobalBaseReg() { +SDNode *PPCDAGToDAGISel::getGlobalBaseReg() { if (!GlobalBaseReg) { // Insert the set of GlobalBaseReg into the first MBB of the function MachineBasicBlock &FirstMBB = BB->getParent()->front(); @@ -267,7 +267,7 @@ SDOperand PPCDAGToDAGISel::getGlobalBaseReg() { BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR); BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg); } - return CurDAG->getRegister(GlobalBaseReg, PPCLowering.getPointerTy()); + return CurDAG->getRegister(GlobalBaseReg, PPCLowering.getPointerTy()).Val; } /// isIntS16Immediate - This method tests to see if the node is either a 32-bit @@ -902,20 +902,18 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDOperand Op) { // Select - Convert the specified operand from a target-independent to a // target-specific node if it hasn't already been changed. -SDNode *PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { +SDNode *PPCDAGToDAGISel::Select(SDOperand Op) { SDNode *N = Op.Val; if (N->getOpcode() >= ISD::BUILTIN_OP_END && - N->getOpcode() < PPCISD::FIRST_NUMBER) { - Result = Op; + N->getOpcode() < PPCISD::FIRST_NUMBER) return NULL; // Already selected. - } switch (N->getOpcode()) { default: break; case ISD::SETCC: return SelectSETCC(Op); case PPCISD::GlobalBaseReg: - return getGlobalBaseReg().Val; + return getGlobalBaseReg(); case ISD::FrameIndex: { int FI = cast<FrameIndexSDNode>(N)->getIndex(); @@ -1118,7 +1116,7 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { case PPCISD::CALL: return MySelect_PPCcall(Op); } - return SelectCode(Result, Op); + return SelectCode(Op); } diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp index cb5ff8b..7c298c7 100644 --- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp +++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp @@ -966,7 +966,7 @@ public: Subtarget(TM.getSubtarget<SparcSubtarget>()) { } - SDNode *Select(SDOperand &Result, SDOperand Op); + SDNode *Select(SDOperand Op); // Complex Pattern Selectors. bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2); @@ -1063,13 +1063,11 @@ bool SparcDAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1, return true; } -SDNode *SparcDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { +SDNode *SparcDAGToDAGISel::Select(SDOperand Op) { SDNode *N = Op.Val; if (N->getOpcode() >= ISD::BUILTIN_OP_END && - N->getOpcode() < SPISD::FIRST_NUMBER) { - Result = Op; + N->getOpcode() < SPISD::FIRST_NUMBER) return NULL; // Already selected. - } switch (N->getOpcode()) { default: break; @@ -1113,7 +1111,7 @@ SDNode *SparcDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { } } - return SelectCode(Result, Op); + return SelectCode(Op); } diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp index abe7627..6ec294c 100644 --- a/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -123,7 +123,7 @@ namespace { #include "X86GenDAGISel.inc" private: - SDNode *Select(SDOperand &Result, SDOperand N); + SDNode *Select(SDOperand N); bool MatchAddress(SDOperand N, X86ISelAddressMode &AM, bool isRoot = true); bool SelectAddr(SDOperand N, SDOperand &Base, SDOperand &Scale, @@ -176,7 +176,7 @@ namespace { /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC /// base register. Return the virtual register that holds this value. - SDOperand getGlobalBaseReg(); + SDNode *getGlobalBaseReg(); #ifndef NDEBUG unsigned Indent; @@ -582,7 +582,7 @@ static bool isRegister0(SDOperand Op) { /// getGlobalBaseReg - Output the instructions required to put the /// base address to use for accessing globals into a register. /// -SDOperand X86DAGToDAGISel::getGlobalBaseReg() { +SDNode *X86DAGToDAGISel::getGlobalBaseReg() { if (!GlobalBaseReg) { // Insert the set of GlobalBaseReg into the first MBB of the function MachineBasicBlock &FirstMBB = BB->getParent()->front(); @@ -594,7 +594,7 @@ SDOperand X86DAGToDAGISel::getGlobalBaseReg() { BuildMI(FirstMBB, MBBI, X86::MovePCtoStack, 0); BuildMI(FirstMBB, MBBI, X86::POP32r, 1, GlobalBaseReg); } - return CurDAG->getRegister(GlobalBaseReg, MVT::i32); + return CurDAG->getRegister(GlobalBaseReg, MVT::i32).Val; } static SDNode *FindCallStartFromCall(SDNode *Node) { @@ -604,7 +604,7 @@ static SDNode *FindCallStartFromCall(SDNode *Node) { return FindCallStartFromCall(Node->getOperand(0).Val); } -SDNode *X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) { +SDNode *X86DAGToDAGISel::Select(SDOperand N) { SDNode *Node = N.Val; MVT::ValueType NVT = Node->getValueType(0); unsigned Opc, MOpc; @@ -619,7 +619,6 @@ SDNode *X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) { #endif if (Opcode >= ISD::BUILTIN_OP_END && Opcode < X86ISD::FIRST_NUMBER) { - Result = N; #ifndef NDEBUG DEBUG(std::cerr << std::string(Indent-2, ' ')); DEBUG(std::cerr << "== "); @@ -633,8 +632,7 @@ SDNode *X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) { switch (Opcode) { default: break; case X86ISD::GlobalBaseReg: - Result = getGlobalBaseReg(); - return Result.Val; + return getGlobalBaseReg(); case ISD::ADD: { // Turn ADD X, c to MOV32ri X+c. This cannot be done with tblgen'd @@ -736,7 +734,7 @@ SDNode *X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) { SDOperand(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0); } - Result = CurDAG->getCopyFromReg(Chain, HiReg, NVT, InFlag); + SDOperand Result = CurDAG->getCopyFromReg(Chain, HiReg, NVT, InFlag); ReplaceUses(N.getValue(0), Result); if (foldedLoad) ReplaceUses(N1.getValue(1), Result.getValue(1)); @@ -840,8 +838,8 @@ SDNode *X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) { SDOperand(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0); } - Result = CurDAG->getCopyFromReg(Chain, isDiv ? LoReg : HiReg, - NVT, InFlag); + SDOperand Result = CurDAG->getCopyFromReg(Chain, isDiv ? LoReg : HiReg, + NVT, InFlag); ReplaceUses(N.getValue(0), Result); if (foldedLoad) ReplaceUses(N1.getValue(1), Result.getValue(1)); @@ -878,28 +876,31 @@ SDNode *X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) { AddToISelQueue(Node->getOperand(0)); SDOperand Tmp = SDOperand(CurDAG->getTargetNode(Opc, VT, Node->getOperand(0)), 0); - Result = SDOperand(CurDAG->getTargetNode(Opc2, NVT, Tmp), 0); + SDNode *ResNode = CurDAG->getTargetNode(Opc2, NVT, Tmp); #ifndef NDEBUG DEBUG(std::cerr << std::string(Indent-2, ' ')); DEBUG(std::cerr << "=> "); - DEBUG(Result.Val->dump(CurDAG)); + DEBUG(ResNode->dump(CurDAG)); DEBUG(std::cerr << "\n"); Indent -= 2; #endif - return Result.Val; + return ResNode; } break; } } - SDNode *ResNode = SelectCode(Result, N); + SDNode *ResNode = SelectCode(N); #ifndef NDEBUG DEBUG(std::cerr << std::string(Indent-2, ' ')); DEBUG(std::cerr << "=> "); - DEBUG(Result.Val->dump(CurDAG)); + if (ResNode == NULL || ResNode == N.Val) + DEBUG(N.Val->dump(CurDAG)); + else + DEBUG(ResNode->dump(CurDAG)); DEBUG(std::cerr << "\n"); Indent -= 2; #endif |