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author | Mon P Wang <wangmp@apple.com> | 2008-12-12 01:25:51 +0000 |
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committer | Mon P Wang <wangmp@apple.com> | 2008-12-12 01:25:51 +0000 |
commit | 9e5ecb8f8f3b639874b943702a3dd1d0739bb9b9 (patch) | |
tree | 6c753c8554523a437a141254e13ab1c72875aff3 /lib | |
parent | ab55ebda1c2254f98b06e770bc2dae7d05a4a366 (diff) | |
download | external_llvm-9e5ecb8f8f3b639874b943702a3dd1d0739bb9b9.zip external_llvm-9e5ecb8f8f3b639874b943702a3dd1d0739bb9b9.tar.gz external_llvm-9e5ecb8f8f3b639874b943702a3dd1d0739bb9b9.tar.bz2 |
Added support for SELECT v8i8 v4i16 for X86 (MMX)
Added support for TRUNC v8i16 to v8i8 for X86 (MMX)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60916 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 4 | ||||
-rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 8 | ||||
-rw-r--r-- | lib/Target/X86/X86InstrMMX.td | 11 |
3 files changed, 23 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 405aec6..2108abf 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -3937,6 +3937,10 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { if (Tmp1.getNode()) Result = Tmp1; } break; + case TargetLowering::Expand: + assert(Result.getValueType().isVector() && "must be vector type"); + // Unroll the truncate. We should do better. + Result = LegalizeOp(UnrollVectorOp(Result)); } break; case Expand: diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 496112d..fd57ccf 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -650,6 +650,13 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom); setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom); + + setTruncStoreAction(MVT::v8i16, MVT::v8i8, Expand); + setOperationAction(ISD::TRUNCATE, MVT::v8i8, Expand); + setOperationAction(ISD::SELECT, MVT::v8i8, Promote); + setOperationAction(ISD::SELECT, MVT::v4i16, Promote); + setOperationAction(ISD::SELECT, MVT::v2i32, Promote); + setOperationAction(ISD::SELECT, MVT::v1i64, Custom); } if (Subtarget->hasSSE1()) { @@ -6960,6 +6967,7 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); switch (MI->getOpcode()) { default: assert(false && "Unexpected instr type to insert"); + case X86::CMOV_V1I64: case X86::CMOV_FR32: case X86::CMOV_FR64: case X86::CMOV_V4F32: diff --git a/lib/Target/X86/X86InstrMMX.td b/lib/Target/X86/X86InstrMMX.td index fd70801..62055c0 100644 --- a/lib/Target/X86/X86InstrMMX.td +++ b/lib/Target/X86/X86InstrMMX.td @@ -681,3 +681,14 @@ def : Pat<(v8i8 (bitconvert (i64 (vector_extract (v2i64 VR128:$src), (iPTR 0))))), (v8i8 (MMX_MOVDQ2Qrr VR128:$src))>; +// CMOV* - Used to implement the SELECT DAG operation. Expanded by the +// scheduler into a branch sequence. +// These are expanded by the scheduler. +let Uses = [EFLAGS], usesCustomDAGSchedInserter = 1 in { + def CMOV_V1I64 : I<0, Pseudo, + (outs VR64:$dst), (ins VR64:$t, VR64:$f, i8imm:$cond), + "#CMOV_V1I64 PSEUDO!", + [(set VR64:$dst, + (v1i64 (X86cmov VR64:$t, VR64:$f, imm:$cond, + EFLAGS)))]>; +} |