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author | Brian Gaeke <gaeke@uiuc.edu> | 2004-11-22 08:02:06 +0000 |
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committer | Brian Gaeke <gaeke@uiuc.edu> | 2004-11-22 08:02:06 +0000 |
commit | 9ffcf9fdddf6e11ed59a70d440408d305a42436d (patch) | |
tree | d1f8651b6c78021372904ff5276291dc3a22b59e /lib | |
parent | 6f0b77221cb9bd82a7ac8b4551f69fab6a03eceb (diff) | |
download | external_llvm-9ffcf9fdddf6e11ed59a70d440408d305a42436d.zip external_llvm-9ffcf9fdddf6e11ed59a70d440408d305a42436d.tar.gz external_llvm-9ffcf9fdddf6e11ed59a70d440408d305a42436d.tar.bz2 |
Add stub method for long shift codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18100 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/Target/Sparc/SparcV8ISelSimple.cpp | 21 | ||||
-rw-r--r-- | lib/Target/SparcV8/SparcV8ISelSimple.cpp | 21 |
2 files changed, 42 insertions, 0 deletions
diff --git a/lib/Target/Sparc/SparcV8ISelSimple.cpp b/lib/Target/Sparc/SparcV8ISelSimple.cpp index f30db1b..2144be6 100644 --- a/lib/Target/Sparc/SparcV8ISelSimple.cpp +++ b/lib/Target/Sparc/SparcV8ISelSimple.cpp @@ -90,6 +90,9 @@ namespace { MachineBasicBlock::iterator IP, unsigned DestReg, const char *FuncName, unsigned Op0Reg, unsigned Op1Reg); + void emitShift64 (MachineBasicBlock *MBB, MachineBasicBlock::iterator IP, + Instruction &I, unsigned DestReg, unsigned Op0Reg, + unsigned Op1Reg); void visitBinaryOperator(Instruction &I); void visitShiftInst (ShiftInst &SI) { visitBinaryOperator (SI); } void visitSetCondInst(SetCondInst &I); @@ -1109,6 +1112,20 @@ void V8ISel::emitOp64LibraryCall (MachineBasicBlock *MBB, BuildMI (*MBB, IP, V8::ORrr, 2, DestReg+1).addReg (V8::G0).addReg (V8::O1); } +void V8ISel::emitShift64 (MachineBasicBlock *MBB, + MachineBasicBlock::iterator IP, Instruction &I, + unsigned DestReg, unsigned Op0Reg, unsigned Op1Reg) { + bool isSigned = I.getType()->isSigned(); + + switch (I.getOpcode ()) { + case Instruction::Shl: + case Instruction::Shr: + default: + std::cerr << "Sorry, 64-bit shifts are not yet supported:\n" << I; + abort (); + } +} + void V8ISel::visitBinaryOperator (Instruction &I) { unsigned DestReg = getReg (I); unsigned Op0Reg = getReg (I.getOperand (0)); @@ -1168,6 +1185,10 @@ void V8ISel::visitBinaryOperator (Instruction &I) { FuncName = I.getType ()->isSigned () ? "__rem64" : "__urem64"; emitOp64LibraryCall (BB, BB->end (), DestReg, FuncName, Op0Reg, Op1Reg); return; + case Instruction::Shl: + case Instruction::Shr: + emitShift64 (BB, BB->end (), I, DestReg, Op0Reg, Op1Reg); + return; } } diff --git a/lib/Target/SparcV8/SparcV8ISelSimple.cpp b/lib/Target/SparcV8/SparcV8ISelSimple.cpp index f30db1b..2144be6 100644 --- a/lib/Target/SparcV8/SparcV8ISelSimple.cpp +++ b/lib/Target/SparcV8/SparcV8ISelSimple.cpp @@ -90,6 +90,9 @@ namespace { MachineBasicBlock::iterator IP, unsigned DestReg, const char *FuncName, unsigned Op0Reg, unsigned Op1Reg); + void emitShift64 (MachineBasicBlock *MBB, MachineBasicBlock::iterator IP, + Instruction &I, unsigned DestReg, unsigned Op0Reg, + unsigned Op1Reg); void visitBinaryOperator(Instruction &I); void visitShiftInst (ShiftInst &SI) { visitBinaryOperator (SI); } void visitSetCondInst(SetCondInst &I); @@ -1109,6 +1112,20 @@ void V8ISel::emitOp64LibraryCall (MachineBasicBlock *MBB, BuildMI (*MBB, IP, V8::ORrr, 2, DestReg+1).addReg (V8::G0).addReg (V8::O1); } +void V8ISel::emitShift64 (MachineBasicBlock *MBB, + MachineBasicBlock::iterator IP, Instruction &I, + unsigned DestReg, unsigned Op0Reg, unsigned Op1Reg) { + bool isSigned = I.getType()->isSigned(); + + switch (I.getOpcode ()) { + case Instruction::Shl: + case Instruction::Shr: + default: + std::cerr << "Sorry, 64-bit shifts are not yet supported:\n" << I; + abort (); + } +} + void V8ISel::visitBinaryOperator (Instruction &I) { unsigned DestReg = getReg (I); unsigned Op0Reg = getReg (I.getOperand (0)); @@ -1168,6 +1185,10 @@ void V8ISel::visitBinaryOperator (Instruction &I) { FuncName = I.getType ()->isSigned () ? "__rem64" : "__urem64"; emitOp64LibraryCall (BB, BB->end (), DestReg, FuncName, Op0Reg, Op1Reg); return; + case Instruction::Shl: + case Instruction::Shr: + emitShift64 (BB, BB->end (), I, DestReg, Op0Reg, Op1Reg); + return; } } |