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| author | Eric Christopher <echristo@apple.com> | 2009-07-23 02:22:41 +0000 |
|---|---|---|
| committer | Eric Christopher <echristo@apple.com> | 2009-07-23 02:22:41 +0000 |
| commit | a0443603dc856d5143643598b0e28bdc2d3b33e8 (patch) | |
| tree | 58c77fa1c2c5a9f660503d58950fbc49dba7f126 /lib | |
| parent | 1c6577924c122bad21e2794fa3b580899ef4127e (diff) | |
| download | external_llvm-a0443603dc856d5143643598b0e28bdc2d3b33e8.zip external_llvm-a0443603dc856d5143643598b0e28bdc2d3b33e8.tar.gz external_llvm-a0443603dc856d5143643598b0e28bdc2d3b33e8.tar.bz2 | |
Support insertps via the intrinsic and add a couple of simple
testcases to make sure it's being generated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76843 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 5d6ef36..2c9a064 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -3590,15 +3590,19 @@ let Constraints = "$src1 = $dst" in { defm PINSRD : SS41I_insert32<0x22, "pinsrd">; +// insertps has a few different modes, there's the first two here below which +// are optimized inserts that won't zero arbitrary elements in the destination +// vector. The next one matches the intrinsic and could zero arbitrary elements +// in the target vector. let Constraints = "$src1 = $dst" in { multiclass SS41I_insertf32<bits<8> opc, string OpcodeStr> { - def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst), + def match_rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, FR32:$src2, i32i8imm:$src3), !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), [(set VR128:$dst, (X86insrtps VR128:$src1, FR32:$src2, imm:$src3))]>, OpSize; - def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst), + def match_rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3), !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), @@ -3608,6 +3612,14 @@ let Constraints = "$src1 = $dst" in { } } +let Constraints = "$src1 = $dst" in { + def INSERTPSrr : SS4AIi8<0x21, MRMSrcReg, (outs VR128:$dst), + (ins VR128:$src1, VR128:$src2, i32i8imm:$src3), + "insertps\t{$src3, $src2, $dst|$dst, $src2, $src3}", + [(set VR128:$dst, (int_x86_sse41_insertps VR128:$src1, + VR128:$src2, imm:$src3))]>; +} + defm INSERTPS : SS41I_insertf32<0x21, "insertps">; let Defs = [EFLAGS] in { |