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| author | Johnny Chen <johnny.chen@apple.com> | 2010-03-09 21:39:34 +0000 |
|---|---|---|
| committer | Johnny Chen <johnny.chen@apple.com> | 2010-03-09 21:39:34 +0000 |
| commit | a2c618a0f08a331e3f45bd5108423b084c2986ed (patch) | |
| tree | 46cd788b4aec432eaa35b183a2e91786bafac9fe /lib | |
| parent | f3a066f7c3ef4e729c92929acab352a93f8d7563 (diff) | |
| download | external_llvm-a2c618a0f08a331e3f45bd5108423b084c2986ed.zip external_llvm-a2c618a0f08a331e3f45bd5108423b084c2986ed.tar.gz external_llvm-a2c618a0f08a331e3f45bd5108423b084c2986ed.tar.bz2 | |
MSR (Move to Special Register from ARM core register) requires a mask to specify
what fields of the CPSR or SPSR are affected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98085 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 16 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrThumb2.td | 8 |
2 files changed, 12 insertions, 12 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 3a5c8ab..af82a5f 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -2844,29 +2844,29 @@ def MRSsys : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary,"mrs","\t$dst, spsr", let Inst{7-4} = 0b0000; } -// FIXME: mask is ignored for the time being. -def MSR : ABI<0b0001,(outs),(ins GPR:$src), NoItinerary, "msr", "\tcpsr, $src", +def MSR : ABI<0b0001, (outs), (ins GPR:$src, i32imm:$mask), NoItinerary, "msr", + "\tcpsr${mask:msr}, $src", [/* For disassembly only; pattern left blank */]> { let Inst{23-20} = 0b0010; let Inst{7-4} = 0b0000; } -// FIXME: mask is ignored for the time being. -def MSRi : ABI<0b0011,(outs),(ins so_imm:$a), NoItinerary, "msr", "\tcpsr, $a", +def MSRi : ABI<0b0011, (outs), (ins so_imm:$a, i32imm:$mask), NoItinerary,"msr", + "\tcpsr${mask:msr}, $a", [/* For disassembly only; pattern left blank */]> { let Inst{23-20} = 0b0010; let Inst{7-4} = 0b0000; } -// FIXME: mask is ignored for the time being. -def MSRsys : ABI<0b0001,(outs),(ins GPR:$src),NoItinerary,"msr","\tspsr, $src", +def MSRsys : ABI<0b0001, (outs), (ins GPR:$src, i32imm:$mask),NoItinerary,"msr", + "\tspsr${mask:msr}, $src", [/* For disassembly only; pattern left blank */]> { let Inst{23-20} = 0b0110; let Inst{7-4} = 0b0000; } -// FIXME: mask is ignored for the time being. -def MSRsysi : ABI<0b0011,(outs),(ins so_imm:$a),NoItinerary,"msr","\tspsr, $a", +def MSRsysi : ABI<0b0011,(outs),(ins so_imm:$a, i32imm:$mask),NoItinerary,"msr", + "\tspsr${mask:msr}, $a", [/* For disassembly only; pattern left blank */]> { let Inst{23-20} = 0b0110; let Inst{7-4} = 0b0000; diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index 77714bb..2fc7d2f 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -2637,9 +2637,9 @@ def t2MRSsys : T2I<(outs GPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, spsr", let Inst{12} = 0; } -// FIXME: mask is ignored for the time being. // Rn = Inst{19-16} -def t2MSR : T2I<(outs), (ins GPR:$src), NoItinerary, "msr", "\tcpsr, $src", +def t2MSR : T2I<(outs), (ins GPR:$src, i32imm:$mask), NoItinerary, "msr", + "\tcpsr${mask:msr}, $src", [/* For disassembly only; pattern left blank */]> { let Inst{31-27} = 0b11110; let Inst{26} = 0; @@ -2649,9 +2649,9 @@ def t2MSR : T2I<(outs), (ins GPR:$src), NoItinerary, "msr", "\tcpsr, $src", let Inst{12} = 0; } -// FIXME: mask is ignored for the time being. // Rn = Inst{19-16} -def t2MSRsys : T2I<(outs), (ins GPR:$src), NoItinerary, "msr", "\tspsr, $src", +def t2MSRsys : T2I<(outs), (ins GPR:$src, i32imm:$mask), NoItinerary, "msr", + "\tspsr${mask:msr}, $src", [/* For disassembly only; pattern left blank */]> { let Inst{31-27} = 0b11110; let Inst{26} = 0; |