diff options
| author | Chris Lattner <sabre@nondot.org> | 2004-04-07 04:26:57 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2004-04-07 04:26:57 +0000 |
| commit | a562efce355618a02a23ebd3e26d277b26d4e8d5 (patch) | |
| tree | d4ca672e1bd7a66fb00e0e77c026dc6cbfd66af5 /lib | |
| parent | 6a135f2e8cb2a3ce291ea7adc73cc0fc50b8ed1c (diff) | |
| download | external_llvm-a562efce355618a02a23ebd3e26d277b26d4e8d5.zip external_llvm-a562efce355618a02a23ebd3e26d277b26d4e8d5.tar.gz external_llvm-a562efce355618a02a23ebd3e26d277b26d4e8d5.tar.bz2 | |
Fix encoding of existing shift instructions, add rr shifts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12739 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/Sparc/SparcInstrInfo.td | 9 | ||||
| -rw-r--r-- | lib/Target/SparcV8/SparcV8InstrInfo.td | 9 |
2 files changed, 12 insertions, 6 deletions
diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td index ae4e9e6..8764d4e 100644 --- a/lib/Target/Sparc/SparcInstrInfo.td +++ b/lib/Target/Sparc/SparcInstrInfo.td @@ -83,9 +83,12 @@ def XORrr : F3_1<2, 0b000011, "xor">; def XORri : F3_2<2, 0b000011, "xor">; // Section B.12 - Shift Instructions, p. 107 -def SLLri : F3_1<2, 0b100101, "sll">; -def SRLri : F3_1<2, 0b100110, "srl">; -def SRAri : F3_1<2, 0b100111, "sra">; +def SLLrr : F3_1<2, 0b100101, "sll">; +def SLLri : F3_2<2, 0b100101, "sll">; +def SRLrr : F3_1<2, 0b100110, "srl">; +def SRLri : F3_2<2, 0b100110, "srl">; +def SRArr : F3_1<2, 0b100111, "sra">; +def SRAri : F3_2<2, 0b100111, "sra">; // Section B.13 - Add Instructions, p. 108 def ADDrr : F3_1<2, 0b000000, "add">; diff --git a/lib/Target/SparcV8/SparcV8InstrInfo.td b/lib/Target/SparcV8/SparcV8InstrInfo.td index ae4e9e6..8764d4e 100644 --- a/lib/Target/SparcV8/SparcV8InstrInfo.td +++ b/lib/Target/SparcV8/SparcV8InstrInfo.td @@ -83,9 +83,12 @@ def XORrr : F3_1<2, 0b000011, "xor">; def XORri : F3_2<2, 0b000011, "xor">; // Section B.12 - Shift Instructions, p. 107 -def SLLri : F3_1<2, 0b100101, "sll">; -def SRLri : F3_1<2, 0b100110, "srl">; -def SRAri : F3_1<2, 0b100111, "sra">; +def SLLrr : F3_1<2, 0b100101, "sll">; +def SLLri : F3_2<2, 0b100101, "sll">; +def SRLrr : F3_1<2, 0b100110, "srl">; +def SRLri : F3_2<2, 0b100110, "srl">; +def SRArr : F3_1<2, 0b100111, "sra">; +def SRAri : F3_2<2, 0b100111, "sra">; // Section B.13 - Add Instructions, p. 108 def ADDrr : F3_1<2, 0b000000, "add">; |