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author | Bill Wendling <isanbard@gmail.com> | 2008-03-24 23:16:37 +0000 |
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committer | Bill Wendling <isanbard@gmail.com> | 2008-03-24 23:16:37 +0000 |
commit | a77e9f0453ee449a486019e9de21f8ebd1e74efe (patch) | |
tree | 170b010898def458df8645a03735dc44fb9f1db2 /lib | |
parent | 7db979944d0020335a72a72a1d182b0f381c2ede (diff) | |
download | external_llvm-a77e9f0453ee449a486019e9de21f8ebd1e74efe.zip external_llvm-a77e9f0453ee449a486019e9de21f8ebd1e74efe.tar.gz external_llvm-a77e9f0453ee449a486019e9de21f8ebd1e74efe.tar.bz2 |
Use the bit size of the operand instead of the hard-coded 32 to generate the
mask.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48750 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.cpp | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 5a3a51f..5cf08a6 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -822,8 +822,10 @@ bool PPCTargetLowering::SelectAddressRegImm(SDOperand N, SDOperand &Disp, // provably disjoint. APInt LHSKnownZero, LHSKnownOne; DAG.ComputeMaskedBits(N.getOperand(0), - APInt::getAllOnesValue(32), + APInt::getAllOnesValue(N.getOperand(0) + .getValueSizeInBits()), LHSKnownZero, LHSKnownOne); + if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { // If all of the bits are known zero on the LHS or RHS, the add won't // carry. @@ -932,7 +934,8 @@ bool PPCTargetLowering::SelectAddressRegImmShift(SDOperand N, SDOperand &Disp, // provably disjoint. APInt LHSKnownZero, LHSKnownOne; DAG.ComputeMaskedBits(N.getOperand(0), - APInt::getAllOnesValue(32), + APInt::getAllOnesValue(N.getOperand(0) + .getValueSizeInBits()), LHSKnownZero, LHSKnownOne); if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { // If all of the bits are known zero on the LHS or RHS, the add won't |