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| author | Evan Cheng <evan.cheng@apple.com> | 2008-04-01 01:50:16 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2008-04-01 01:50:16 +0000 |
| commit | a87400339fcb3e087996e7ad534816d640c8b716 (patch) | |
| tree | 8e2d5ff1fe6379310c785a3ec7a2c40f65b24369 /lib | |
| parent | 9ab553f2bf985473d2d0fb451e8a6ff53212203d (diff) | |
| download | external_llvm-a87400339fcb3e087996e7ad534816d640c8b716.zip external_llvm-a87400339fcb3e087996e7ad534816d640c8b716.tar.gz external_llvm-a87400339fcb3e087996e7ad534816d640c8b716.tar.bz2 | |
Unbreak ARM / Thumb soft FP support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49012 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 14 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 16 |
2 files changed, 21 insertions, 9 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 0d629db..78c0263 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -5450,7 +5450,14 @@ ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { } RTLIB::Libcall LC; - if (SourceVT == MVT::i64) { + if (SourceVT == MVT::i32) { + if (DestTy == MVT::f32) + LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32; + else { + assert(DestTy == MVT::f64 && "Unknown fp value type!"); + LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64; + } + } else if (SourceVT == MVT::i64) { if (DestTy == MVT::f32) LC = RTLIB::SINTTOFP_I64_F32; else if (DestTy == MVT::f64) @@ -5481,7 +5488,7 @@ ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { SDOperand HiPart; SDOperand Result = ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned, HiPart); - if (Result.getValueType() != DestTy) + if (Result.getValueType() != DestTy && HiPart.Val) Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart); return Result; } @@ -6773,7 +6780,8 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT, Node->getOperand(0)); - ExpandOp(Lo, Lo, Hi); + if (getTypeAction(Lo.getValueType()) == Expand) + ExpandOp(Lo, Lo, Hi); break; } } diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 421a03f..7218560 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -248,16 +248,20 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) setOperationAction(ISD::FCOS , MVT::f64, Expand); setOperationAction(ISD::FREM , MVT::f64, Expand); setOperationAction(ISD::FREM , MVT::f32, Expand); - setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); - setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); + if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) { + setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); + setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); + } setOperationAction(ISD::FPOW , MVT::f64, Expand); setOperationAction(ISD::FPOW , MVT::f32, Expand); // int <-> fp are custom expanded into bit_convert + ARMISD ops. - setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); - setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); - setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); - setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); + if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) { + setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); + setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); + setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); + setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); + } // We have target-specific dag combine patterns for the following nodes: // ARMISD::FMRRD - No need to call setTargetDAGCombine |