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| author | Craig Topper <craig.topper@gmail.com> | 2013-08-30 07:16:16 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2013-08-30 07:16:16 +0000 |
| commit | a9080653c22d6fcacca5878603167151d8d11ee4 (patch) | |
| tree | 8725a8b1b861f22ce903445abfed1c86936724a9 /lib | |
| parent | 74f269176fb3b3dc2d3d6417492c65ef28a8ecfa (diff) | |
| download | external_llvm-a9080653c22d6fcacca5878603167151d8d11ee4.zip external_llvm-a9080653c22d6fcacca5878603167151d8d11ee4.tar.gz external_llvm-a9080653c22d6fcacca5878603167151d8d11ee4.tar.bz2 | |
Fixup BZHI selection to remove an unneeded zero extension.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189656 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 6 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrInfo.td | 22 |
2 files changed, 15 insertions, 13 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index ecbd24f..73c4a1c 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -17320,8 +17320,7 @@ static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG, assert(N001.getValueType() == MVT::i8 && "unexpected type"); ConstantSDNode *C = dyn_cast<ConstantSDNode>(N00.getOperand(0)); if (C && C->getZExtValue() == 1) - return DAG.getNode(X86ISD::BZHI, DL, VT, N1, - DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N001)); + return DAG.getNode(X86ISD::BZHI, DL, VT, N1, N001); } } @@ -17333,8 +17332,7 @@ static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG, assert(N101.getValueType() == MVT::i8 && "unexpected type"); ConstantSDNode *C = dyn_cast<ConstantSDNode>(N10.getOperand(0)); if (C && C->getZExtValue() == 1) - return DAG.getNode(X86ISD::BZHI, DL, VT, N0, - DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N101)); + return DAG.getNode(X86ISD::BZHI, DL, VT, N0, N101); } } } diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index fca7d4c..869b9e0 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -252,7 +252,7 @@ def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags, def X86blsi : SDNode<"X86ISD::BLSI", SDTIntUnaryOp>; def X86blsmsk : SDNode<"X86ISD::BLSMSK", SDTIntUnaryOp>; def X86blsr : SDNode<"X86ISD::BLSR", SDTIntUnaryOp>; -def X86bzhi : SDNode<"X86ISD::BZHI", SDTIntBinOp>; +def X86bzhi : SDNode<"X86ISD::BZHI", SDTIntShiftOp>; def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>; @@ -1856,14 +1856,18 @@ let Predicates = [HasBMI2], Defs = [EFLAGS] in { int_x86_bmi_bzhi_64, loadi64>, VEX_W; } -def : Pat<(X86bzhi GR32:$src1, GR32:$src2), - (BZHI32rr GR32:$src1, GR32:$src2)>; -def : Pat<(X86bzhi (loadi32 addr:$src1), GR32:$src2), - (BZHI32rm addr:$src1, GR32:$src2)>; -def : Pat<(X86bzhi GR64:$src1, GR64:$src2), - (BZHI64rr GR64:$src1, GR64:$src2)>; -def : Pat<(X86bzhi (loadi64 addr:$src1), GR64:$src2), - (BZHI64rm addr:$src1, GR64:$src2)>; +def : Pat<(X86bzhi GR32:$src1, GR8:$src2), + (BZHI32rr GR32:$src1, + (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; +def : Pat<(X86bzhi (loadi32 addr:$src1), GR8:$src2), + (BZHI32rm addr:$src1, + (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; +def : Pat<(X86bzhi GR64:$src1, GR8:$src2), + (BZHI64rr GR64:$src1, + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; +def : Pat<(X86bzhi (loadi64 addr:$src1), GR8:$src2), + (BZHI64rm addr:$src1, + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC, X86MemOperand x86memop, Intrinsic Int, |