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| author | Chris Lattner <sabre@nondot.org> | 2010-11-14 18:09:50 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2010-11-14 18:09:50 +0000 |
| commit | b0269cd2c8d8512ea156a6c6df798faa6c76145c (patch) | |
| tree | 0994f9db20efea07c36b7799a96997400959d83f /lib | |
| parent | cd6636c737a82949ad13db2d0d918af6424fb78b (diff) | |
| download | external_llvm-b0269cd2c8d8512ea156a6c6df798faa6c76145c.zip external_llvm-b0269cd2c8d8512ea156a6c6df798faa6c76145c.tar.gz external_llvm-b0269cd2c8d8512ea156a6c6df798faa6c76145c.tar.bz2 | |
random acts of tidiness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119049 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/X86/X86RegisterInfo.td | 15 |
1 files changed, 5 insertions, 10 deletions
diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td index 959c01e..8fc26d7 100644 --- a/lib/Target/X86/X86RegisterInfo.td +++ b/lib/Target/X86/X86RegisterInfo.td @@ -453,19 +453,16 @@ def GR64 : RegisterClass<"X86", [i64], 64, // Segment registers for use by MOV instructions (and others) that have a // segment register as one operand. Always contain a 16-bit segment // descriptor. -def SEGMENT_REG : RegisterClass<"X86", [i16], 16, [CS, DS, SS, ES, FS, GS]> { -} +def SEGMENT_REG : RegisterClass<"X86", [i16], 16, [CS, DS, SS, ES, FS, GS]>; // Debug registers. def DEBUG_REG : RegisterClass<"X86", [i32], 32, - [DR0, DR1, DR2, DR3, DR4, DR5, DR6, DR7]> { -} + [DR0, DR1, DR2, DR3, DR4, DR5, DR6, DR7]>; // Control registers. def CONTROL_REG : RegisterClass<"X86", [i64], 64, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7, CR8, - CR9, CR10, CR11, CR12, CR13, CR14, CR15]> { -} + CR9, CR10, CR11, CR12, CR13, CR14, CR15]>; // GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD, GR32_ABCD, GR64_ABCD - Subclasses of // GR8, GR16, GR32, and GR64 which contain just the "a" "b", "c", and "d" @@ -473,10 +470,8 @@ def CONTROL_REG : RegisterClass<"X86", [i64], 64, // that support 8-bit subreg operations. On x86-64, GR16_ABCD, GR32_ABCD, // and GR64_ABCD are classes for registers that support 8-bit h-register // operations. -def GR8_ABCD_L : RegisterClass<"X86", [i8], 8, [AL, CL, DL, BL]> { -} -def GR8_ABCD_H : RegisterClass<"X86", [i8], 8, [AH, CH, DH, BH]> { -} +def GR8_ABCD_L : RegisterClass<"X86", [i8], 8, [AL, CL, DL, BL]>; +def GR8_ABCD_H : RegisterClass<"X86", [i8], 8, [AH, CH, DH, BH]>; def GR16_ABCD : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]> { let SubRegClasses = [(GR8_ABCD_L sub_8bit), (GR8_ABCD_H sub_8bit_hi)]; } |