[SystemZ] Add STOC and STOCG

These instructions are allowed to trap even if the condition is false,
so for now they are only used for "*ptr = (cond ? x : *ptr)"-style
constructs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187111 91177308-0d34-0410-b5e6-96231b3b80d8

7 files changed, 126 insertions, 51 deletions

diff --git a/lib/Target/SystemZ/SystemZISelLowering.cpp b/lib/Target/SystemZ/SystemZISelLowering.cpp
index e6e6d02..e70f775 100644
--- a/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -1773,22 +1773,36 @@ SystemZTargetLowering::emitSelect(MachineInstr *MI,
 
 // Implement EmitInstrWithCustomInserter for pseudo CondStore* instruction MI.
 // StoreOpcode is the store to use and Invert says whether the store should
-// happen when the condition is false rather than true.
+// happen when the condition is false rather than true.  If a STORE ON
+// CONDITION is available, STOCOpcode is its opcode, otherwise it is 0.
 MachineBasicBlock *
 SystemZTargetLowering::emitCondStore(MachineInstr *MI,
                                      MachineBasicBlock *MBB,
-                                     unsigned StoreOpcode, bool Invert) const {
+                                     unsigned StoreOpcode, unsigned STOCOpcode,
+                                     bool Invert) const {
   const SystemZInstrInfo *TII = TM.getInstrInfo();
 
-  MachineOperand Base = MI->getOperand(0);
-  int64_t Disp        = MI->getOperand(1).getImm();
-  unsigned IndexReg   = MI->getOperand(2).getReg();
-  unsigned SrcReg     = MI->getOperand(3).getReg();
+  unsigned SrcReg     = MI->getOperand(0).getReg();
+  MachineOperand Base = MI->getOperand(1);
+  int64_t Disp        = MI->getOperand(2).getImm();
+  unsigned IndexReg   = MI->getOperand(3).getReg();
   unsigned CCMask     = MI->getOperand(4).getImm();
   DebugLoc DL         = MI->getDebugLoc();
 
   StoreOpcode = TII->getOpcodeForOffset(StoreOpcode, Disp);
 
+  // Use STOCOpcode if possible.  We could use different store patterns in
+  // order to avoid matching the index register, but the performance trade-offs
+  // might be more complicated in that case.
+  if (STOCOpcode && !IndexReg && TM.getSubtargetImpl()->hasLoadStoreOnCond()) {
+    if (Invert)
+      CCMask = CCMask ^ SystemZ::CCMASK_ANY;
+    BuildMI(*MBB, MI, DL, TII->get(STOCOpcode))
+      .addReg(SrcReg).addOperand(Base).addImm(Disp).addImm(CCMask);
+    MI->eraseFromParent();
+    return MBB;
+  }
+
   // Get the condition needed to branch around the store.
   if (!Invert)
     CCMask = CCMask ^ SystemZ::CCMASK_ANY;
@@ -2249,41 +2263,41 @@ EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const {
     return emitSelect(MI, MBB);
 
   case SystemZ::CondStore8_32:
-    return emitCondStore(MI, MBB, SystemZ::STC32, false);
+    return emitCondStore(MI, MBB, SystemZ::STC32, 0, false);
   case SystemZ::CondStore8_32Inv:
-    return emitCondStore(MI, MBB, SystemZ::STC32, true);
+    return emitCondStore(MI, MBB, SystemZ::STC32, 0, true);
   case SystemZ::CondStore16_32:
-    return emitCondStore(MI, MBB, SystemZ::STH32, false);
+    return emitCondStore(MI, MBB, SystemZ::STH32, 0, false);
   case SystemZ::CondStore16_32Inv:
-    return emitCondStore(MI, MBB, SystemZ::STH32, true);
+    return emitCondStore(MI, MBB, SystemZ::STH32, 0, true);
   case SystemZ::CondStore32_32:
-    return emitCondStore(MI, MBB, SystemZ::ST32, false);
+    return emitCondStore(MI, MBB, SystemZ::ST32, SystemZ::STOC32, false);
   case SystemZ::CondStore32_32Inv:
-    return emitCondStore(MI, MBB, SystemZ::ST32, true);
+    return emitCondStore(MI, MBB, SystemZ::ST32, SystemZ::STOC32, true);
   case SystemZ::CondStore8:
-    return emitCondStore(MI, MBB, SystemZ::STC, false);
+    return emitCondStore(MI, MBB, SystemZ::STC, 0, false);
   case SystemZ::CondStore8Inv:
-    return emitCondStore(MI, MBB, SystemZ::STC, true);
+    return emitCondStore(MI, MBB, SystemZ::STC, 0, true);
   case SystemZ::CondStore16:
-    return emitCondStore(MI, MBB, SystemZ::STH, false);
+    return emitCondStore(MI, MBB, SystemZ::STH, 0, false);
   case SystemZ::CondStore16Inv:
-    return emitCondStore(MI, MBB, SystemZ::STH, true);
+    return emitCondStore(MI, MBB, SystemZ::STH, 0, true);
   case SystemZ::CondStore32:
-    return emitCondStore(MI, MBB, SystemZ::ST, false);
+    return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, false);
   case SystemZ::CondStore32Inv:
-    return emitCondStore(MI, MBB, SystemZ::ST, true);
+    return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, true);
   case SystemZ::CondStore64:
-    return emitCondStore(MI, MBB, SystemZ::STG, false);
+    return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, false);
   case SystemZ::CondStore64Inv:
-    return emitCondStore(MI, MBB, SystemZ::STG, true);
+    return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, true);
   case SystemZ::CondStoreF32:
-    return emitCondStore(MI, MBB, SystemZ::STE, false);
+    return emitCondStore(MI, MBB, SystemZ::STE, 0, false);
   case SystemZ::CondStoreF32Inv:
-    return emitCondStore(MI, MBB, SystemZ::STE, true);
+    return emitCondStore(MI, MBB, SystemZ::STE, 0, true);
   case SystemZ::CondStoreF64:
-    return emitCondStore(MI, MBB, SystemZ::STD, false);
+    return emitCondStore(MI, MBB, SystemZ::STD, 0, false);
   case SystemZ::CondStoreF64Inv:
-    return emitCondStore(MI, MBB, SystemZ::STD, true);
+    return emitCondStore(MI, MBB, SystemZ::STD, 0, true);
 
   case SystemZ::AEXT128_64:
     return emitExt128(MI, MBB, false, SystemZ::subreg_low);
diff --git a/lib/Target/SystemZ/SystemZISelLowering.h b/lib/Target/SystemZ/SystemZISelLowering.h
index 88e1fa7..ce876a9 100644
--- a/lib/Target/SystemZ/SystemZISelLowering.h
+++ b/lib/Target/SystemZ/SystemZISelLowering.h
@@ -211,7 +211,8 @@ private:
                                 MachineBasicBlock *BB) const;
   MachineBasicBlock *emitCondStore(MachineInstr *MI,
                                    MachineBasicBlock *BB,
-                                   unsigned StoreOpcode, bool Invert) const;
+                                   unsigned StoreOpcode, unsigned STOCOpcode,
+                                   bool Invert) const;
   MachineBasicBlock *emitExt128(MachineInstr *MI,
                                 MachineBasicBlock *MBB,
                                 bool ClearEven, unsigned SubReg) const;
diff --git a/lib/Target/SystemZ/SystemZInstrFormats.td b/lib/Target/SystemZ/SystemZInstrFormats.td
index 9257a6a..b92c350 100644
--- a/lib/Target/SystemZ/SystemZInstrFormats.td
+++ b/lib/Target/SystemZ/SystemZInstrFormats.td
@@ -451,9 +451,11 @@ class InstSS<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 // Instruction definitions with semantics
 //===----------------------------------------------------------------------===//
 //
-// These classes have the form <Category><Format>, where <Format> is one
+// These classes have the form [Cond]<Category><Format>, where <Format> is one
 // of the formats defined above and where <Category> describes the inputs
-// and outputs.  <Category> can be one of:
+// and outputs.  "Cond" is used if the instruction is conditional,
+// in which case the 4-bit condition-code mask is added as a final operand.
+// <Category> can be one of:
 //
 //   Inherent:
 //     One register output operand and no input operands.
@@ -618,6 +620,40 @@ multiclass StoreSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
   }
 }
 
+class CondStoreRSY<string mnemonic, bits<16> opcode,
+                   RegisterOperand cls, bits<5> bytes,
+                   AddressingMode mode = bdaddr20only>
+  : InstRSY<opcode, (outs), (ins cls:$R1, mode:$BD2, cond4:$R3),
+            mnemonic#"$R3\t$R1, $BD2", []>,
+    Requires<[FeatureLoadStoreOnCond]> {
+  let mayStore = 1;
+  let AccessBytes = bytes;
+}
+
+// Like CondStoreRSY, but used for the raw assembly form.  The condition-code
+// mask is the third operand rather than being part of the mnemonic.
+class AsmCondStoreRSY<string mnemonic, bits<16> opcode,
+                      RegisterOperand cls, bits<5> bytes,
+                      AddressingMode mode = bdaddr20only>
+  : InstRSY<opcode, (outs), (ins cls:$R1, mode:$BD2, uimm8zx4:$R3),
+            mnemonic#"\t$R1, $BD2, $R3", []>,
+    Requires<[FeatureLoadStoreOnCond]> {
+  let mayStore = 1;
+  let AccessBytes = bytes;
+}
+
+// Like CondStoreRSY, but with a fixed CC mask.
+class FixedCondStoreRSY<string mnemonic, bits<16> opcode,
+                        RegisterOperand cls, bits<4> ccmask, bits<5> bytes,
+                        AddressingMode mode = bdaddr20only>
+  : InstRSY<opcode, (outs), (ins cls:$R1, mode:$BD2),
+            mnemonic#"\t$R1, $BD2", []>,
+    Requires<[FeatureLoadStoreOnCond]> {
+  let mayStore = 1;
+  let AccessBytes = bytes;
+  let R3 = ccmask;
+}
+
 class UnaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
               RegisterOperand cls1, RegisterOperand cls2>
   : InstRR<opcode, (outs cls1:$R1), (ins cls2:$R2),
@@ -1151,12 +1187,12 @@ class SelectWrapper<RegisterOperand cls>
 multiclass CondStores<RegisterOperand cls, SDPatternOperator store,
                       SDPatternOperator load, AddressingMode mode> {
   let Defs = [CC], Uses = [CC], usesCustomInserter = 1 in {
-    def "" : Pseudo<(outs), (ins mode:$addr, cls:$new, i8imm:$cc),
+    def "" : Pseudo<(outs), (ins cls:$new, mode:$addr, uimm8zx4:$cc),
                     [(store (z_select_ccmask cls:$new, (load mode:$addr),
-                                             imm:$cc), mode:$addr)]>;
-    def Inv : Pseudo<(outs), (ins mode:$addr, cls:$new, i8imm:$cc),
+                                             uimm8zx4:$cc), mode:$addr)]>;
+    def Inv : Pseudo<(outs), (ins cls:$new, mode:$addr, uimm8zx4:$cc),
                      [(store (z_select_ccmask (load mode:$addr), cls:$new,
-                                              imm:$cc), mode:$addr)]>;
+                                              uimm8zx4:$cc), mode:$addr)]>;
   }
 }
 
diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td
index 56b7a1f..bda34df 100644
--- a/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -107,26 +107,28 @@ defm AsmC : CompareBranches<uimm8zx4, "", "$M3, ">;
 // (integer or floating-point)
 multiclass CondExtendedMnemonic<bits<4> ccmask, string name> {
   let R1 = ccmask in {
-    def "" : InstRI<0xA74, (outs), (ins brtarget16:$I2),
-                    "j"##name##"\t$I2", []>;
-    def L  : InstRIL<0xC04, (outs), (ins brtarget32:$I2),
+    def J : InstRI<0xA74, (outs), (ins brtarget16:$I2),
+                   "j"##name##"\t$I2", []>;
+    def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2),
                      "jg"##name##"\t$I2", []>;
   }
+  def STOC  : FixedCondStoreRSY<"stoc"##name,  0xEBF3, GR32, ccmask, 4>;
+  def STOCG : FixedCondStoreRSY<"stocg"##name, 0xEBE3, GR64, ccmask, 8>;
 }
-defm AsmJO   : CondExtendedMnemonic<1,  "o">;
-defm AsmJH   : CondExtendedMnemonic<2,  "h">;
-defm AsmJNLE : CondExtendedMnemonic<3,  "nle">;
-defm AsmJL   : CondExtendedMnemonic<4,  "l">;
-defm AsmJNHE : CondExtendedMnemonic<5,  "nhe">;
-defm AsmJLH  : CondExtendedMnemonic<6,  "lh">;
-defm AsmJNE  : CondExtendedMnemonic<7,  "ne">;
-defm AsmJE   : CondExtendedMnemonic<8,  "e">;
-defm AsmJNLH : CondExtendedMnemonic<9,  "nlh">;
-defm AsmJHE  : CondExtendedMnemonic<10, "he">;
-defm AsmJNL  : CondExtendedMnemonic<11, "nl">;
-defm AsmJLE  : CondExtendedMnemonic<12, "le">;
-defm AsmJNH  : CondExtendedMnemonic<13, "nh">;
-defm AsmJNO  : CondExtendedMnemonic<14, "no">;
+defm AsmO   : CondExtendedMnemonic<1,  "o">;
+defm AsmH   : CondExtendedMnemonic<2,  "h">;
+defm AsmNLE : CondExtendedMnemonic<3,  "nle">;
+defm AsmL   : CondExtendedMnemonic<4,  "l">;
+defm AsmNHE : CondExtendedMnemonic<5,  "nhe">;
+defm AsmLH  : CondExtendedMnemonic<6,  "lh">;
+defm AsmNE  : CondExtendedMnemonic<7,  "ne">;
+defm AsmE   : CondExtendedMnemonic<8,  "e">;
+defm AsmNLH : CondExtendedMnemonic<9,  "nlh">;
+defm AsmHE  : CondExtendedMnemonic<10, "he">;
+defm AsmNL  : CondExtendedMnemonic<11, "nl">;
+defm AsmLE  : CondExtendedMnemonic<12, "le">;
+defm AsmNH  : CondExtendedMnemonic<13, "nh">;
+defm AsmNO  : CondExtendedMnemonic<14, "no">;
 
 // Define AsmParser mnemonics for each integer condition-code mask.
 // This is like the list above, except that condition 3 is not possible
@@ -274,6 +276,17 @@ let isCodeGenOnly = 1 in
   def STRL32 : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>;
 def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>;
 
+// Store on condition.
+let isCodeGenOnly = 1, Uses = [CC] in {
+  def STOC32 : CondStoreRSY<"stoc",  0xEBF3, GR32, 4>;
+  def STOC   : CondStoreRSY<"stoc",  0xEBF3, GR64, 4>;
+  def STOCG  : CondStoreRSY<"stocg", 0xEBE3, GR64, 8>;
+}
+let Uses = [CC] in {
+  def AsmSTOC  : AsmCondStoreRSY<"stoc",  0xEBF3, GR32, 4>;
+  def AsmSTOCG : AsmCondStoreRSY<"stocg", 0xEBE3, GR64, 8>;
+}
+
 // 8-bit immediate stores to 8-bit fields.
 defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>;
 
diff --git a/lib/Target/SystemZ/SystemZProcessors.td b/lib/Target/SystemZ/SystemZProcessors.td
index 5668ae3..96fa6a4 100644
--- a/lib/Target/SystemZ/SystemZProcessors.td
+++ b/lib/Target/SystemZ/SystemZProcessors.td
@@ -21,6 +21,13 @@ def FeatureDistinctOps : SystemZFeature<
   "Assume that the distinct-operands facility is installed"
 >;
 
+def FeatureLoadStoreOnCond : SystemZFeature<
+  "load-store-on-cond", "LoadStoreOnCond",
+  "Assume that the load/store-on-condition facility is installed"
+>;
+
 def : Processor<"z10",   NoItineraries, []>;
-def : Processor<"z196",  NoItineraries, [FeatureDistinctOps]>;
-def : Processor<"zEC12", NoItineraries, [FeatureDistinctOps]>;
+def : Processor<"z196",  NoItineraries,
+                [FeatureDistinctOps, FeatureLoadStoreOnCond]>;
+def : Processor<"zEC12", NoItineraries,
+                [FeatureDistinctOps, FeatureLoadStoreOnCond]>;
diff --git a/lib/Target/SystemZ/SystemZSubtarget.cpp b/lib/Target/SystemZ/SystemZSubtarget.cpp
index f37ea21..43ac1ea 100644
--- a/lib/Target/SystemZ/SystemZSubtarget.cpp
+++ b/lib/Target/SystemZ/SystemZSubtarget.cpp
@@ -21,7 +21,7 @@ SystemZSubtarget::SystemZSubtarget(const std::string &TT,
                                    const std::string &CPU,
                                    const std::string &FS)
   : SystemZGenSubtargetInfo(TT, CPU, FS), HasDistinctOps(false),
-    TargetTriple(TT) {
+    HasLoadStoreOnCond(false), TargetTriple(TT) {
   std::string CPUName = CPU;
   if (CPUName.empty())
     CPUName = "z10";
diff --git a/lib/Target/SystemZ/SystemZSubtarget.h b/lib/Target/SystemZ/SystemZSubtarget.h
index 4a86287..9d5dfc8a 100644
--- a/lib/Target/SystemZ/SystemZSubtarget.h
+++ b/lib/Target/SystemZ/SystemZSubtarget.h
@@ -28,6 +28,7 @@ class StringRef;
 class SystemZSubtarget : public SystemZGenSubtargetInfo {
 protected:
   bool HasDistinctOps;
+  bool HasLoadStoreOnCond;
 
 private:
   Triple TargetTriple;
@@ -42,6 +43,9 @@ public:
   // Return true if the target has the distinct-operands facility.
   bool hasDistinctOps() const { return HasDistinctOps; }
 
+  // Return true if the target has the load/store-on-condition facility.
+  bool hasLoadStoreOnCond() const { return HasLoadStoreOnCond; }
+
   // Return true if GV can be accessed using LARL for reloc model RM
   // and code model CM.
   bool isPC32DBLSymbol(const GlobalValue *GV, Reloc::Model RM,