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| author | Jim Grosbach <grosbach@apple.com> | 2011-10-24 23:40:46 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-10-24 23:40:46 +0000 |
| commit | b36e03d987c843ccb731627ffd2b1db17bd72e39 (patch) | |
| tree | c9009a0576d97a618d89ae195a297994f2fa149b /lib | |
| parent | 5921675ff5ea632ab1e6d7aa5d1f263b858bbafa (diff) | |
| download | external_llvm-b36e03d987c843ccb731627ffd2b1db17bd72e39.zip external_llvm-b36e03d987c843ccb731627ffd2b1db17bd72e39.tar.gz external_llvm-b36e03d987c843ccb731627ffd2b1db17bd72e39.tar.bz2 | |
Nuke dead code. Nothing generates the VLD1d64QPseudo_UPD instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142877 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/ARM/ARMBaseInstrInfo.cpp | 1 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMExpandPseudoInsts.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrNEON.td | 1 |
3 files changed, 0 insertions, 4 deletions
diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp index caa500c..23fae3e 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -2610,7 +2610,6 @@ ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, case ARM::VLD4d8Pseudo_UPD: case ARM::VLD4d16Pseudo_UPD: case ARM::VLD4d32Pseudo_UPD: - case ARM::VLD1d64QPseudo_UPD: case ARM::VLD4q8Pseudo_UPD: case ARM::VLD4q16Pseudo_UPD: case ARM::VLD4q32Pseudo_UPD: diff --git a/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/lib/Target/ARM/ARMExpandPseudoInsts.cpp index 459ba0a..d1ee635 100644 --- a/lib/Target/ARM/ARMExpandPseudoInsts.cpp +++ b/lib/Target/ARM/ARMExpandPseudoInsts.cpp @@ -143,7 +143,6 @@ static const NEONLdStTableEntry NEONLdStTable[] = { { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, EvenDblSpc, 1, 8 ,true}, { ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, SingleSpc, 4, 1 ,false}, -{ ARM::VLD1d64QPseudo_UPD, ARM::VLD1d64Q_UPD, true, true, SingleSpc, 4, 1 ,false}, { ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, SingleSpc, 3, 1 ,false}, { ARM::VLD1q16Pseudo, ARM::VLD1q16, true, false, SingleSpc, 2, 4 ,false}, { ARM::VLD1q16PseudoWB_fixed, ARM::VLD1q16wb_fixed,true,false,SingleSpc, 2, 4 ,false}, @@ -1113,7 +1112,6 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB, case ARM::VLD4d8Pseudo_UPD: case ARM::VLD4d16Pseudo_UPD: case ARM::VLD4d32Pseudo_UPD: - case ARM::VLD1d64QPseudo_UPD: case ARM::VLD4q8Pseudo_UPD: case ARM::VLD4q16Pseudo_UPD: case ARM::VLD4q32Pseudo_UPD: diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td index c280d61..9d0350b 100644 --- a/lib/Target/ARM/ARMInstrNEON.td +++ b/lib/Target/ARM/ARMInstrNEON.td @@ -444,7 +444,6 @@ def VLD1d32Q_UPD : VLD1D4WB<{1,0,?,?}, "32">; def VLD1d64Q_UPD : VLD1D4WB<{1,1,?,?}, "64">; def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD1x4>; -def VLD1d64QPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x4u>; // VLD2 : Vector Load (multiple 2-element structures) class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy> |