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| author | Kevin Enderby <enderby@apple.com> | 2010-03-19 20:04:42 +0000 |
|---|---|---|
| committer | Kevin Enderby <enderby@apple.com> | 2010-03-19 20:04:42 +0000 |
| commit | b46b03b36f50c11d5517024c1d0ef3763085eb90 (patch) | |
| tree | fa58b47ce4c6975803ed714e91a9bc69a75b1e6a /lib | |
| parent | 80d23705e6df49a41298fd345be6f8a8d72f4fd0 (diff) | |
| download | external_llvm-b46b03b36f50c11d5517024c1d0ef3763085eb90.zip external_llvm-b46b03b36f50c11d5517024c1d0ef3763085eb90.tar.gz external_llvm-b46b03b36f50c11d5517024c1d0ef3763085eb90.tar.bz2 | |
Fixed the encoding problems of the crc32 instructions. All had the Operand size
override prefix and only the r/m16 forms should have had that. Also for variant
one, the AT&T syntax, added suffixes to all forms. Also added the missing
64-bit form for 'CRC32 r64, r/m8'. Plus added test cases for all forms and
tweaked one test case to add the needed suffixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98980 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 51 |
1 files changed, 31 insertions, 20 deletions
diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 1c00a36..720b663 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -3823,54 +3823,65 @@ def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))), let Constraints = "$src1 = $dst" in { def CRC32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i8mem:$src2), - "crc32 \t{$src2, $src1|$src1, $src2}", + "crc32{b} \t{$src2, $src1|$src1, $src2}", [(set GR32:$dst, (int_x86_sse42_crc32_8 GR32:$src1, - (load addr:$src2)))]>, OpSize; + (load addr:$src2)))]>; def CRC32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR8:$src2), - "crc32 \t{$src2, $src1|$src1, $src2}", + "crc32{b} \t{$src2, $src1|$src1, $src2}", [(set GR32:$dst, - (int_x86_sse42_crc32_8 GR32:$src1, GR8:$src2))]>, - OpSize; + (int_x86_sse42_crc32_8 GR32:$src1, GR8:$src2))]>; def CRC32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i16mem:$src2), - "crc32 \t{$src2, $src1|$src1, $src2}", + "crc32{w} \t{$src2, $src1|$src1, $src2}", [(set GR32:$dst, (int_x86_sse42_crc32_16 GR32:$src1, (load addr:$src2)))]>, OpSize; def CRC32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR16:$src2), - "crc32 \t{$src2, $src1|$src1, $src2}", + "crc32{w} \t{$src2, $src1|$src1, $src2}", [(set GR32:$dst, (int_x86_sse42_crc32_16 GR32:$src1, GR16:$src2))]>, OpSize; def CRC32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), - "crc32 \t{$src2, $src1|$src1, $src2}", + "crc32{l} \t{$src2, $src1|$src1, $src2}", [(set GR32:$dst, (int_x86_sse42_crc32_32 GR32:$src1, - (load addr:$src2)))]>, OpSize; + (load addr:$src2)))]>; def CRC32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), - "crc32 \t{$src2, $src1|$src1, $src2}", + "crc32{l} \t{$src2, $src1|$src1, $src2}", [(set GR32:$dst, - (int_x86_sse42_crc32_32 GR32:$src1, GR32:$src2))]>, - OpSize; - def CRC64m64 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst), + (int_x86_sse42_crc32_32 GR32:$src1, GR32:$src2))]>; + def CRC64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst), + (ins GR64:$src1, i8mem:$src2), + "crc32{b} \t{$src2, $src1|$src1, $src2}", + [(set GR64:$dst, + (int_x86_sse42_crc64_8 GR64:$src1, + (load addr:$src2)))]>, + REX_W; + def CRC64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst), + (ins GR64:$src1, GR8:$src2), + "crc32{b} \t{$src2, $src1|$src1, $src2}", + [(set GR64:$dst, + (int_x86_sse42_crc64_8 GR64:$src1, GR8:$src2))]>, + REX_W; + def CRC64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), - "crc32 \t{$src2, $src1|$src1, $src2}", + "crc32{q} \t{$src2, $src1|$src1, $src2}", [(set GR64:$dst, - (int_x86_sse42_crc32_64 GR64:$src1, + (int_x86_sse42_crc64_64 GR64:$src1, (load addr:$src2)))]>, - OpSize, REX_W; - def CRC64r64 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst), + REX_W; + def CRC64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), - "crc32 \t{$src2, $src1|$src1, $src2}", + "crc32{q} \t{$src2, $src1|$src1, $src2}", [(set GR64:$dst, - (int_x86_sse42_crc32_64 GR64:$src1, GR64:$src2))]>, - OpSize, REX_W; + (int_x86_sse42_crc64_64 GR64:$src1, GR64:$src2))]>, + REX_W; } // String/text processing instructions. |