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| author | Christopher Lamb <christopher.lamb@gmail.com> | 2007-07-26 07:34:40 +0000 |
|---|---|---|
| committer | Christopher Lamb <christopher.lamb@gmail.com> | 2007-07-26 07:34:40 +0000 |
| commit | b768c2edff5a647884e01ba70f2a940053ba49c8 (patch) | |
| tree | 090da8652cbe31564bd456dd9b7c54d3e36aeb43 /lib | |
| parent | 07b222fe9c26c415c0da81f20e5049a2497a9695 (diff) | |
| download | external_llvm-b768c2edff5a647884e01ba70f2a940053ba49c8.zip external_llvm-b768c2edff5a647884e01ba70f2a940053ba49c8.tar.gz external_llvm-b768c2edff5a647884e01ba70f2a940053ba49c8.tar.bz2 | |
Add selection DAG nodes for subreg insert/extract. PR1350
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40516 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 18 | ||||
| -rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 5 | ||||
| -rw-r--r-- | lib/Target/TargetSelectionDAG.td | 5 |
3 files changed, 26 insertions, 2 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 25f0320..4131ed9 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -957,7 +957,23 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { AddLegalizedOperand(SDOperand(Node, i), Tmp1); } return Tmp2; - + case ISD::EXTRACT_SUBREG: { + Tmp1 = LegalizeOp(Node->getOperand(0)); + ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1)); + assert(idx && "Operand must be a constant"); + Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0)); + Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); + } + break; + case ISD::INSERT_SUBREG: { + Tmp1 = LegalizeOp(Node->getOperand(0)); + Tmp2 = LegalizeOp(Node->getOperand(1)); + ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2)); + assert(idx && "Operand must be a constant"); + Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0)); + Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); + } + break; case ISD::BUILD_VECTOR: switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { default: assert(0 && "This action is not supported yet!"); diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 9b146ee..d4d984b 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -3455,7 +3455,10 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const { case ISD::SHL_PARTS: return "shl_parts"; case ISD::SRA_PARTS: return "sra_parts"; case ISD::SRL_PARTS: return "srl_parts"; - + + case ISD::EXTRACT_SUBREG: return "extract_subreg"; + case ISD::INSERT_SUBREG: return "insert_subreg"; + // Conversion operators. case ISD::SIGN_EXTEND: return "sign_extend"; case ISD::ZERO_EXTEND: return "zero_extend"; diff --git a/lib/Target/TargetSelectionDAG.td b/lib/Target/TargetSelectionDAG.td index 491bb02..4b6d881 100644 --- a/lib/Target/TargetSelectionDAG.td +++ b/lib/Target/TargetSelectionDAG.td @@ -317,6 +317,11 @@ def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>; def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT", SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>; + +def extract_subreg : SDNode<"ISD::EXTRACT_SUBREG", + SDTypeProfile<1, 2, []>>; +def insert_subreg : SDNode<"ISD::INSERT_SUBREG", + SDTypeProfile<1, 3, []>>; // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use // these internally. Don't reference these directly. |