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| author | Chris Lattner <sabre@nondot.org> | 2003-09-10 19:52:54 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2003-09-10 19:52:54 +0000 |
| commit | b787e13e736da92378129bbe807e2501018539cb (patch) | |
| tree | 7050a033fc54d774933fa9700c5ed9b0b18776f9 /lib | |
| parent | b3aad5d28f12344424787f983654ca46fa9d7e73 (diff) | |
| download | external_llvm-b787e13e736da92378129bbe807e2501018539cb.zip external_llvm-b787e13e736da92378129bbe807e2501018539cb.tar.gz external_llvm-b787e13e736da92378129bbe807e2501018539cb.tar.bz2 | |
Be a little more specific about what is begin generated. Only print
command line if VERBOSE=1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8453 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/X86/Makefile | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/lib/Target/X86/Makefile b/lib/Target/X86/Makefile index 84f168a..87522ec 100644 --- a/lib/Target/X86/Makefile +++ b/lib/Target/X86/Makefile @@ -8,28 +8,28 @@ $(SourceDepend): X86GenRegisterInfo.h.inc X86GenRegisterNames.inc \ X86GenInstrInfo.inc X86GenInstrSelector.inc X86GenRegisterNames.inc:: X86.td X86RegisterInfo.td ../Target.td $(TBLGEN) - @echo "Tblgen'ing $<" - $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@ + @echo "Building $< register names with tblgen" + $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@ X86GenRegisterInfo.h.inc:: X86.td X86RegisterInfo.td ../Target.td $(TBLGEN) - @echo "Tblgen'ing $<" - $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@ + @echo "Building $< register information header with tblgen" + $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@ X86GenRegisterInfo.inc:: X86.td X86RegisterInfo.td ../Target.td $(TBLGEN) - @echo "Tblgen'ing $<" - $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@ + @echo "Building $< register information implementation with tblgen" + $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@ X86GenInstrNames.inc:: X86.td X86InstrInfo.td ../Target.td $(TBLGEN) - @echo "Tblgen'ing $<" - $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@ + @echo "Building $< instruction names with tblgen" + $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@ X86GenInstrInfo.inc:: X86.td X86InstrInfo.td ../Target.td $(TBLGEN) - @echo "Tblgen'ing $<" - $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@ + @echo "Building $< instruction information with tblgen" + $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@ X86GenInstrSelector.inc:: X86.td X86InstrInfo.td ../Target.td $(TBLGEN) - @echo "Tblgen'ing $<" - $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-selector -o $@ + @echo "Building $< instruction selector with tblgen" + $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-selector -o $@ clean:: $(VERB) rm -f *.inc |