Fix command-line option printing to print two spaces where needed,

instead of requiring all "short description" strings to begin with
two spaces. This makes these strings less mysterious, and it fixes
some cases where short description strings mistakenly did not
begin with two spaces.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57521 91177308-0d34-0410-b5e6-96231b3b80d8

25 files changed, 40 insertions, 40 deletions

diff --git a/lib/CodeGen/RegAllocBigBlock.cpp b/lib/CodeGen/RegAllocBigBlock.cpp
index 0bc9538..68c7936 100644
--- a/lib/CodeGen/RegAllocBigBlock.cpp
+++ b/lib/CodeGen/RegAllocBigBlock.cpp
@@ -53,7 +53,7 @@ STATISTIC(NumLoads , "Number of loads added");
 STATISTIC(NumFolded, "Number of loads/stores folded into instructions");
 
 static RegisterRegAlloc
-  bigBlockRegAlloc("bigblock", "  Big-block register allocator",
+  bigBlockRegAlloc("bigblock", "Big-block register allocator",
                 createBigBlockRegisterAllocator);
 
 namespace {
diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp
index 31e47f9..ede387e 100644
--- a/lib/CodeGen/RegAllocLinearScan.cpp
+++ b/lib/CodeGen/RegAllocLinearScan.cpp
@@ -50,7 +50,7 @@ NewHeuristic("new-spilling-heuristic",
              cl::init(false), cl::Hidden);
 
 static RegisterRegAlloc
-linearscanRegAlloc("linearscan", "  linear scan register allocator",
+linearscanRegAlloc("linearscan", "linear scan register allocator",
                    createLinearScanRegisterAllocator);
 
 namespace {
diff --git a/lib/CodeGen/RegAllocLocal.cpp b/lib/CodeGen/RegAllocLocal.cpp
index 4792452..b7df9dd 100644
--- a/lib/CodeGen/RegAllocLocal.cpp
+++ b/lib/CodeGen/RegAllocLocal.cpp
@@ -37,7 +37,7 @@ STATISTIC(NumStores, "Number of stores added");
 STATISTIC(NumLoads , "Number of loads added");
 
 static RegisterRegAlloc
-  localRegAlloc("local", "  local register allocator",
+  localRegAlloc("local", "local register allocator",
                 createLocalRegisterAllocator);
 
 namespace {
diff --git a/lib/CodeGen/RegAllocPBQP.cpp b/lib/CodeGen/RegAllocPBQP.cpp
index 107d277..1aea7e2 100644
--- a/lib/CodeGen/RegAllocPBQP.cpp
+++ b/lib/CodeGen/RegAllocPBQP.cpp
@@ -60,7 +60,7 @@
 using namespace llvm;
 
 static RegisterRegAlloc
-registerPBQPRepAlloc("pbqp", "  PBQP register allocator",
+registerPBQPRepAlloc("pbqp", "PBQP register allocator",
                      createPBQPRegisterAllocator);
 
 
diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp
index da729ae..7dc9890 100644
--- a/lib/CodeGen/RegAllocSimple.cpp
+++ b/lib/CodeGen/RegAllocSimple.cpp
@@ -35,7 +35,7 @@ STATISTIC(NumLoads , "Number of loads added");
 
 namespace {
   static RegisterRegAlloc
-    simpleRegAlloc("simple", "  simple register allocator",
+    simpleRegAlloc("simple", "simple register allocator",
                    createSimpleRegisterAllocator);
 
   class VISIBILITY_HIDDEN RegAllocSimple : public MachineFunctionPass {
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
index ef7e143..83f7b73 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
@@ -31,7 +31,7 @@ STATISTIC(NumDups,       "Number of duplicated nodes");
 STATISTIC(NumCCCopies,   "Number of cross class copies");
 
 static RegisterScheduler
-  fastDAGScheduler("fast", "  Fast suboptimal list scheduling",
+  fastDAGScheduler("fast", "Fast suboptimal list scheduling",
                    createFastDAGScheduler);
 
 namespace {
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
index 4b09b7c..067407b 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
@@ -37,7 +37,7 @@ STATISTIC(NumNoops , "Number of noops inserted");
 STATISTIC(NumStalls, "Number of pipeline stalls");
 
 static RegisterScheduler
-  tdListDAGScheduler("list-td", "  Top-down list scheduler",
+  tdListDAGScheduler("list-td", "Top-down list scheduler",
                      createTDListDAGScheduler);
    
 namespace {
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index 2e22b65..c605292 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -41,11 +41,11 @@ STATISTIC(NumCCCopies,   "Number of cross class copies");
 
 static RegisterScheduler
   burrListDAGScheduler("list-burr",
-                       "  Bottom-up register reduction list scheduling",
+                       "Bottom-up register reduction list scheduling",
                        createBURRListDAGScheduler);
 static RegisterScheduler
   tdrListrDAGScheduler("list-tdrr",
-                       "  Top-down register reduction list scheduling",
+                       "Top-down register reduction list scheduling",
                        createTDRRListDAGScheduler);
 
 namespace {
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index dce46ab..6e9b288 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -119,7 +119,7 @@ ISHeuristic("pre-RA-sched",
                      " allocation):"));
 
 static RegisterScheduler
-defaultListDAGScheduler("default", "  Best scheduler for the target",
+defaultListDAGScheduler("default", "Best scheduler for the target",
                         createDefaultScheduler);
 
 namespace llvm {
diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp
index 26d019b..1c3c139 100644
--- a/lib/CodeGen/VirtRegMap.cpp
+++ b/lib/CodeGen/VirtRegMap.cpp
@@ -56,8 +56,8 @@ static cl::opt<SpillerName>
 SpillerOpt("spiller",
            cl::desc("Spiller to use: (default: local)"),
            cl::Prefix,
-           cl::values(clEnumVal(simple, "  simple spiller"),
-                      clEnumVal(local,  "  local spiller"),
+           cl::values(clEnumVal(simple, "simple spiller"),
+                      clEnumVal(local,  "local spiller"),
                       clEnumValEnd),
            cl::init(local));
 
diff --git a/lib/Support/CommandLine.cpp b/lib/Support/CommandLine.cpp
index 571b033..4981313 100644
--- a/lib/Support/CommandLine.cpp
+++ b/lib/Support/CommandLine.cpp
@@ -953,7 +953,7 @@ void generic_parser_base::printOptionInfo(const Option &O,
     for (unsigned i = 0, e = getNumOptions(); i != e; ++i) {
       size_t NumSpaces = GlobalWidth-strlen(getOption(i))-8;
       cout << "    =" << getOption(i) << std::string(NumSpaces, ' ')
-           << " - " << getDescription(i) << "\n";
+           << " -   " << getDescription(i) << "\n";
     }
   } else {
     if (O.HelpStr[0])
diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp
index 29a9d84..a96e25f 100644
--- a/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/lib/Target/ARM/ARMTargetMachine.cpp
@@ -29,8 +29,8 @@ static cl::opt<bool> DisableIfConversion("disable-arm-if-conversion",cl::Hidden,
                               cl::desc("Disable if-conversion pass"));
 
 // Register the target.
-static RegisterTarget<ARMTargetMachine>   X("arm",   "  ARM");
-static RegisterTarget<ThumbTargetMachine> Y("thumb", "  Thumb");
+static RegisterTarget<ARMTargetMachine>   X("arm",   "ARM");
+static RegisterTarget<ThumbTargetMachine> Y("thumb", "Thumb");
 
 // No assembler printer by default
 ARMTargetMachine::AsmPrinterCtorFn ARMTargetMachine::AsmPrinterCtor = 0;
diff --git a/lib/Target/Alpha/AlphaTargetMachine.cpp b/lib/Target/Alpha/AlphaTargetMachine.cpp
index 15c6948..54bfc05 100644
--- a/lib/Target/Alpha/AlphaTargetMachine.cpp
+++ b/lib/Target/Alpha/AlphaTargetMachine.cpp
@@ -22,7 +22,7 @@
 using namespace llvm;
 
 // Register the targets
-static RegisterTarget<AlphaTargetMachine> X("alpha", "  Alpha (incomplete)");
+static RegisterTarget<AlphaTargetMachine> X("alpha", "Alpha (incomplete)");
 
 const TargetAsmInfo *AlphaTargetMachine::createTargetAsmInfo() const {
   return new AlphaTargetAsmInfo(*this);
diff --git a/lib/Target/CBackend/CBackend.cpp b/lib/Target/CBackend/CBackend.cpp
index 9a79748..7ec649d 100644
--- a/lib/Target/CBackend/CBackend.cpp
+++ b/lib/Target/CBackend/CBackend.cpp
@@ -49,7 +49,7 @@
 using namespace llvm;
 
 // Register the target.
-static RegisterTarget<CTargetMachine> X("c", "  C backend");
+static RegisterTarget<CTargetMachine> X("c", "C backend");
 
 namespace {
   /// CBackendNameAllUsedStructsAndMergeFunctions - This pass inserts names for
diff --git a/lib/Target/CellSPU/SPUTargetMachine.cpp b/lib/Target/CellSPU/SPUTargetMachine.cpp
index f0512f3..b8dd5aa 100644
--- a/lib/Target/CellSPU/SPUTargetMachine.cpp
+++ b/lib/Target/CellSPU/SPUTargetMachine.cpp
@@ -24,7 +24,7 @@ using namespace llvm;
 namespace {
   // Register the targets
   RegisterTarget<SPUTargetMachine>
-  CELLSPU("cellspu", "  STI CBEA Cell SPU");
+  CELLSPU("cellspu", "STI CBEA Cell SPU");
 }
 
 const std::pair<unsigned, int> *
diff --git a/lib/Target/CppBackend/CPPBackend.cpp b/lib/Target/CppBackend/CPPBackend.cpp
index fb83663..95c4ad7 100644
--- a/lib/Target/CppBackend/CPPBackend.cpp
+++ b/lib/Target/CppBackend/CPPBackend.cpp
@@ -72,7 +72,7 @@ static cl::opt<std::string> NameToGenerate("cppfor", cl::Optional,
   cl::init("!bad!"));
 
 // Register the target.
-static RegisterTarget<CPPTargetMachine> X("cpp", "  C++ backend");
+static RegisterTarget<CPPTargetMachine> X("cpp", "C++ backend");
 
 namespace {
   typedef std::vector<const Type*> TypeList;
diff --git a/lib/Target/IA64/IA64TargetMachine.cpp b/lib/Target/IA64/IA64TargetMachine.cpp
index c789a86..1b811b6 100644
--- a/lib/Target/IA64/IA64TargetMachine.cpp
+++ b/lib/Target/IA64/IA64TargetMachine.cpp
@@ -26,7 +26,7 @@ using namespace llvm;
 extern "C" int IA64TargetMachineModule;
 int IA64TargetMachineModule = 0;
 
-static RegisterTarget<IA64TargetMachine> X("ia64", "  IA-64 (Itanium)");
+static RegisterTarget<IA64TargetMachine> X("ia64", "IA-64 (Itanium)");
 
 const TargetAsmInfo *IA64TargetMachine::createTargetAsmInfo() const {
   return new IA64TargetAsmInfo(*this);
diff --git a/lib/Target/MSIL/MSILWriter.cpp b/lib/Target/MSIL/MSILWriter.cpp
index 8e4ca1f..a27c0cc 100644
--- a/lib/Target/MSIL/MSILWriter.cpp
+++ b/lib/Target/MSIL/MSILWriter.cpp
@@ -45,7 +45,7 @@ namespace {
 }
 
 
-static RegisterTarget<MSILTarget> X("msil", "  MSIL backend");
+static RegisterTarget<MSILTarget> X("msil", "MSIL backend");
 
 bool MSILModule::runOnModule(Module &M) {
   ModulePtr = &M;
diff --git a/lib/Target/Mips/MipsTargetMachine.cpp b/lib/Target/Mips/MipsTargetMachine.cpp
index 276868c..25a0eaa 100644
--- a/lib/Target/Mips/MipsTargetMachine.cpp
+++ b/lib/Target/Mips/MipsTargetMachine.cpp
@@ -20,8 +20,8 @@
 using namespace llvm;
 
 // Register the target.
-static RegisterTarget<MipsTargetMachine>    X("mips", "  Mips");
-static RegisterTarget<MipselTargetMachine>  Y("mipsel", "  Mipsel");
+static RegisterTarget<MipsTargetMachine>    X("mips", "Mips");
+static RegisterTarget<MipselTargetMachine>  Y("mipsel", "Mipsel");
 
 const TargetAsmInfo *MipsTargetMachine::
 createTargetAsmInfo() const 
diff --git a/lib/Target/PIC16/PIC16TargetMachine.cpp b/lib/Target/PIC16/PIC16TargetMachine.cpp
index 26b573a..df16469 100644
--- a/lib/Target/PIC16/PIC16TargetMachine.cpp
+++ b/lib/Target/PIC16/PIC16TargetMachine.cpp
@@ -23,7 +23,7 @@ using namespace llvm;
 
 namespace {
   // Register the targets
-  RegisterTarget<PIC16TargetMachine> X("pic16", "  PIC16 14-bit");
+  RegisterTarget<PIC16TargetMachine> X("pic16", "PIC16 14-bit");
 }
 
 PIC16TargetMachine::
diff --git a/lib/Target/PowerPC/PPCTargetMachine.cpp b/lib/Target/PowerPC/PPCTargetMachine.cpp
index 3d73751..22b459c 100644
--- a/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -23,9 +23,9 @@ using namespace llvm;
 
 // Register the targets
 static RegisterTarget<PPC32TargetMachine>
-X("ppc32", "  PowerPC 32");
+X("ppc32", "PowerPC 32");
 static RegisterTarget<PPC64TargetMachine>
-Y("ppc64", "  PowerPC 64");
+Y("ppc64", "PowerPC 64");
 
 // No assembler printer by default
 PPCTargetMachine::AsmPrinterCtorFn PPCTargetMachine::AsmPrinterCtor = 0;
diff --git a/lib/Target/Sparc/SparcTargetMachine.cpp b/lib/Target/Sparc/SparcTargetMachine.cpp
index cc730f8..80af77e 100644
--- a/lib/Target/Sparc/SparcTargetMachine.cpp
+++ b/lib/Target/Sparc/SparcTargetMachine.cpp
@@ -19,7 +19,7 @@
 using namespace llvm;
 
 // Register the target.
-static RegisterTarget<SparcTargetMachine> X("sparc", "  SPARC");
+static RegisterTarget<SparcTargetMachine> X("sparc", "SPARC");
 
 const TargetAsmInfo *SparcTargetMachine::createTargetAsmInfo() const {
   // FIXME: Handle Solaris subtarget someday :)
diff --git a/lib/Target/TargetMachine.cpp b/lib/Target/TargetMachine.cpp
index c05efd0..a1d6fa7 100644
--- a/lib/Target/TargetMachine.cpp
+++ b/lib/Target/TargetMachine.cpp
@@ -102,13 +102,13 @@ DefRelocationModel(
   cl::init(Reloc::Default),
   cl::values(
     clEnumValN(Reloc::Default, "default",
-               "  Target default relocation model"),
+               "Target default relocation model"),
     clEnumValN(Reloc::Static, "static",
-               "  Non-relocatable code"),
+               "Non-relocatable code"),
     clEnumValN(Reloc::PIC_, "pic",
-               "  Fully relocatable, position independent code"),
+               "Fully relocatable, position independent code"),
     clEnumValN(Reloc::DynamicNoPIC, "dynamic-no-pic",
-               "  Relocatable external references, non-relocatable code"),
+               "Relocatable external references, non-relocatable code"),
     clEnumValEnd));
 static cl::opt<llvm::CodeModel::Model, true>
 DefCodeModel(
@@ -118,15 +118,15 @@ DefCodeModel(
   cl::init(CodeModel::Default),
   cl::values(
     clEnumValN(CodeModel::Default, "default",
-               "  Target default code model"),
+               "Target default code model"),
     clEnumValN(CodeModel::Small, "small",
-               "  Small code model"),
+               "Small code model"),
     clEnumValN(CodeModel::Kernel, "kernel",
-               "  Kernel code model"),
+               "Kernel code model"),
     clEnumValN(CodeModel::Medium, "medium",
-               "  Medium code model"),
+               "Medium code model"),
     clEnumValN(CodeModel::Large, "large",
-               "  Large code model"),
+               "Large code model"),
     clEnumValEnd));
 
 static cl::opt<bool, true>
diff --git a/lib/Target/X86/X86Subtarget.cpp b/lib/Target/X86/X86Subtarget.cpp
index 0d90ef6..871e7af 100644
--- a/lib/Target/X86/X86Subtarget.cpp
+++ b/lib/Target/X86/X86Subtarget.cpp
@@ -23,8 +23,8 @@ static cl::opt<X86Subtarget::AsmWriterFlavorTy>
 AsmWriterFlavor("x86-asm-syntax", cl::init(X86Subtarget::Unset),
   cl::desc("Choose style of code to emit from X86 backend:"),
   cl::values(
-    clEnumValN(X86Subtarget::ATT,   "att",   "  Emit AT&T-style assembly"),
-    clEnumValN(X86Subtarget::Intel, "intel", "  Emit Intel-style assembly"),
+    clEnumValN(X86Subtarget::ATT,   "att",   "Emit AT&T-style assembly"),
+    clEnumValN(X86Subtarget::Intel, "intel", "Emit Intel-style assembly"),
     clEnumValEnd));
 
 
diff --git a/lib/Target/X86/X86TargetMachine.cpp b/lib/Target/X86/X86TargetMachine.cpp
index 860868a..923823b 100644
--- a/lib/Target/X86/X86TargetMachine.cpp
+++ b/lib/Target/X86/X86TargetMachine.cpp
@@ -32,9 +32,9 @@ int X86TargetMachineModule = 0;
 
 // Register the target.
 static RegisterTarget<X86_32TargetMachine>
-X("x86",    "  32-bit X86: Pentium-Pro and above");
+X("x86",    "32-bit X86: Pentium-Pro and above");
 static RegisterTarget<X86_64TargetMachine>
-Y("x86-64", "  64-bit X86: EM64T and AMD64");
+Y("x86-64", "64-bit X86: EM64T and AMD64");
 
 // No assembler printer by default
 X86TargetMachine::AsmPrinterCtorFn X86TargetMachine::AsmPrinterCtor = 0;