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author | Evan Cheng <evan.cheng@apple.com> | 2007-09-27 18:46:06 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2007-09-27 18:46:06 +0000 |
commit | bbb220dd6ff7da605c924f87cbe3aa2c1994a524 (patch) | |
tree | 9fb4c8916c8283dc0a8c8d7dda89729534b9e488 /lib | |
parent | 99c4a2c512b355bcf778ea7d7959a6b1469a1a4a (diff) | |
download | external_llvm-bbb220dd6ff7da605c924f87cbe3aa2c1994a524.zip external_llvm-bbb220dd6ff7da605c924f87cbe3aa2c1994a524.tar.gz external_llvm-bbb220dd6ff7da605c924f87cbe3aa2c1994a524.tar.bz2 |
Avoid inserting a live register more than once.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42410 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp | 26 |
1 files changed, 18 insertions, 8 deletions
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index 6127ab6..0b218ab 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -25,6 +25,7 @@ #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Support/Debug.h" #include "llvm/Support/Compiler.h" +#include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallSet.h" #include "llvm/ADT/Statistic.h" #include <climits> @@ -523,17 +524,22 @@ bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU, if (LiveRegs.empty()) return false; + SmallSet<unsigned, 4> RegAdded; // If this node would clobber any "live" register, then it's not ready. for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); I != E; ++I) { if (I->Cost < 0) { unsigned Reg = I->Reg; - if (LiveRegs.count(Reg) && LiveRegDefs[Reg] != I->Dep) - LRegs.push_back(Reg); + if (LiveRegs.count(Reg) && LiveRegDefs[Reg] != I->Dep) { + if (RegAdded.insert(Reg)) + LRegs.push_back(Reg); + } for (const unsigned *Alias = MRI->getAliasSet(Reg); *Alias; ++Alias) - if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != I->Dep) - LRegs.push_back(*Alias); + if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != I->Dep) { + if (RegAdded.insert(*Alias)) + LRegs.push_back(*Alias); + } } } @@ -545,12 +551,16 @@ bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU, if (!TID.ImplicitDefs) continue; for (const unsigned *Reg = TID.ImplicitDefs; *Reg; ++Reg) { - if (LiveRegs.count(*Reg) && LiveRegDefs[*Reg] != SU) - LRegs.push_back(*Reg); + if (LiveRegs.count(*Reg) && LiveRegDefs[*Reg] != SU) { + if (RegAdded.insert(*Reg)) + LRegs.push_back(*Reg); + } for (const unsigned *Alias = MRI->getAliasSet(*Reg); *Alias; ++Alias) - if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != SU) - LRegs.push_back(*Alias); + if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != SU) { + if (RegAdded.insert(*Alias)) + LRegs.push_back(*Alias); + } } } return !LRegs.empty(); |