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author | Bill Wendling <isanbard@gmail.com> | 2010-12-15 01:03:19 +0000 |
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committer | Bill Wendling <isanbard@gmail.com> | 2010-12-15 01:03:19 +0000 |
commit | bc4224bc6bc078b249b030c54f532215f61935c5 (patch) | |
tree | 7abe5650de95b63507f9c99a2ec05e46b3e3648a /lib | |
parent | 415af3452ea85f544761f8947426e4431706a165 (diff) | |
download | external_llvm-bc4224bc6bc078b249b030c54f532215f61935c5.zip external_llvm-bc4224bc6bc078b249b030c54f532215f61935c5.tar.gz external_llvm-bc4224bc6bc078b249b030c54f532215f61935c5.tar.bz2 |
Reapply r121808 now that the missing patterns have been supplied.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121820 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/Target/ARM/ARMISelDAGToDAG.cpp | 37 |
1 files changed, 21 insertions, 16 deletions
diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp index 476fe6e..3e4d72b 100644 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -918,27 +918,15 @@ ARMDAGToDAGISel::SelectThumbAddrModeRI(SDValue N, SDValue &Base, return false; // We want to select tLDRpci instead. } - if (N.getOpcode() != ISD::ADD) { - if (N.getOpcode() == ARMISD::Wrapper && - (!Subtarget->useMovt() || - N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress)) - Base = N.getOperand(0); - else - Base = N; - - Offset = CurDAG->getRegister(0, MVT::i32); - return true; - } + if (N.getOpcode() != ISD::ADD) + return false; // Thumb does not have [sp, r] address mode. RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0)); RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1)); if ((LHSR && LHSR->getReg() == ARM::SP) || - (RHSR && RHSR->getReg() == ARM::SP)) { - Base = N; - Offset = CurDAG->getRegister(0, MVT::i32); - return true; - } + (RHSR && RHSR->getReg() == ARM::SP)) + return false; if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { int RHSC = (int)RHS->getZExtValue(); @@ -1003,6 +991,23 @@ ARMDAGToDAGISel::SelectThumbAddrModeImm5S(SDValue N, unsigned Scale, return true; } + RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0)); + RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1)); + if ((LHSR && LHSR->getReg() == ARM::SP) || + (RHSR && RHSR->getReg() == ARM::SP)) { + ConstantSDNode *LHS = dyn_cast<ConstantSDNode>(N.getOperand(0)); + ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1)); + unsigned LHSC = LHS ? LHS->getZExtValue() : 0; + unsigned RHSC = RHS ? RHS->getZExtValue() : 0; + + // Thumb does not have [sp, #imm5] address mode for non-zero imm5. + if (LHSC != 0 || RHSC != 0) return false; + + Base = N; + OffImm = CurDAG->getTargetConstant(0, MVT::i32); + return true; + } + // If the RHS is + imm5 * scale, fold into addr mode. if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { int RHSC = (int)RHS->getZExtValue(); |