diff options
| author | Edwin Török <edwintorok@gmail.com> | 2009-07-14 16:55:14 +0000 |
|---|---|---|
| committer | Edwin Török <edwintorok@gmail.com> | 2009-07-14 16:55:14 +0000 |
| commit | bd448e3ca993226084d7f53445388fcd8e46b996 (patch) | |
| tree | bf497ec9a02cd2fc0b64e3e58eff037a719a854d /lib | |
| parent | aa2b53498c12c3972f87733108465b59f7cd02a5 (diff) | |
| download | external_llvm-bd448e3ca993226084d7f53445388fcd8e46b996.zip external_llvm-bd448e3ca993226084d7f53445388fcd8e46b996.tar.gz external_llvm-bd448e3ca993226084d7f53445388fcd8e46b996.tar.bz2 | |
llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
166 files changed, 797 insertions, 797 deletions
diff --git a/lib/Analysis/AliasAnalysisCounter.cpp b/lib/Analysis/AliasAnalysisCounter.cpp index 2ed11ac..3eab452 100644 --- a/lib/Analysis/AliasAnalysisCounter.cpp +++ b/lib/Analysis/AliasAnalysisCounter.cpp @@ -132,7 +132,7 @@ AliasAnalysisCounter::alias(const Value *V1, unsigned V1Size, const char *AliasString; switch (R) { - default: LLVM_UNREACHABLE("Unknown alias type!"); + default: llvm_unreachable("Unknown alias type!"); case NoAlias: No++; AliasString = "No alias"; break; case MayAlias: May++; AliasString = "May alias"; break; case MustAlias: Must++; AliasString = "Must alias"; break; @@ -157,7 +157,7 @@ AliasAnalysisCounter::getModRefInfo(CallSite CS, Value *P, unsigned Size) { const char *MRString; switch (R) { - default: LLVM_UNREACHABLE("Unknown mod/ref type!"); + default: llvm_unreachable("Unknown mod/ref type!"); case NoModRef: NoMR++; MRString = "NoModRef"; break; case Ref: JustRef++; MRString = "JustRef"; break; case Mod: JustMod++; MRString = "JustMod"; break; diff --git a/lib/Analysis/AliasSetTracker.cpp b/lib/Analysis/AliasSetTracker.cpp index 7ba98dd..801628e 100644 --- a/lib/Analysis/AliasSetTracker.cpp +++ b/lib/Analysis/AliasSetTracker.cpp @@ -540,7 +540,7 @@ void AliasSet::print(std::ostream &OS) const { case Refs : OS << "Ref "; break; case Mods : OS << "Mod "; break; case ModRef : OS << "Mod/Ref "; break; - default: LLVM_UNREACHABLE("Bad value for AccessTy!"); + default: llvm_unreachable("Bad value for AccessTy!"); } if (isVolatile()) OS << "[volatile] "; if (Forward) diff --git a/lib/Analysis/BasicAliasAnalysis.cpp b/lib/Analysis/BasicAliasAnalysis.cpp index daa3c9a..59839e8 100644 --- a/lib/Analysis/BasicAliasAnalysis.cpp +++ b/lib/Analysis/BasicAliasAnalysis.cpp @@ -158,7 +158,7 @@ namespace { virtual void getArgumentAccesses(Function *F, CallSite CS, std::vector<PointerAccessInfo> &Info) { - LLVM_UNREACHABLE("This method may not be called on this function!"); + llvm_unreachable("This method may not be called on this function!"); } virtual void getMustAliases(Value *P, std::vector<Value*> &RetVals) { } diff --git a/lib/Analysis/ConstantFolding.cpp b/lib/Analysis/ConstantFolding.cpp index 7e6b877..7938ca6 100644 --- a/lib/Analysis/ConstantFolding.cpp +++ b/lib/Analysis/ConstantFolding.cpp @@ -366,7 +366,7 @@ Constant *llvm::ConstantFoldInstOperands(unsigned Opcode, const Type *DestTy, return 0; case Instruction::ICmp: case Instruction::FCmp: - LLVM_UNREACHABLE("This function is invalid for compares: no predicate specified"); + llvm_unreachable("This function is invalid for compares: no predicate specified"); case Instruction::PtrToInt: // If the input is a inttoptr, eliminate the pair. This requires knowing // the width of a pointer, so it can't be done in ConstantExpr::getCast. @@ -691,7 +691,7 @@ static Constant *ConstantFoldFP(double (*NativeFP)(double), double V, return Context->getConstantFP(APFloat((float)V)); if (Ty == Type::DoubleTy) return Context->getConstantFP(APFloat(V)); - LLVM_UNREACHABLE("Can only constant fold float/double"); + llvm_unreachable("Can only constant fold float/double"); return 0; // dummy return to suppress warning } @@ -710,7 +710,7 @@ static Constant *ConstantFoldBinaryFP(double (*NativeFP)(double, double), return Context->getConstantFP(APFloat((float)V)); if (Ty == Type::DoubleTy) return Context->getConstantFP(APFloat(V)); - LLVM_UNREACHABLE("Can only constant fold float/double"); + llvm_unreachable("Can only constant fold float/double"); return 0; // dummy return to suppress warning } diff --git a/lib/Analysis/IPA/Andersens.cpp b/lib/Analysis/IPA/Andersens.cpp index 91aaf06..1fdd87a 100644 --- a/lib/Analysis/IPA/Andersens.cpp +++ b/lib/Analysis/IPA/Andersens.cpp @@ -508,7 +508,7 @@ namespace { #ifndef NDEBUG V->dump(); #endif - LLVM_UNREACHABLE("Value does not have a node in the points-to graph!"); + llvm_unreachable("Value does not have a node in the points-to graph!"); } return I->second; } @@ -827,10 +827,10 @@ unsigned Andersens::getNodeForConstantPointer(Constant *C) { return getNodeForConstantPointer(CE->getOperand(0)); default: cerr << "Constant Expr not yet handled: " << *CE << "\n"; - llvm_unreachable(); + llvm_unreachable(0); } } else { - LLVM_UNREACHABLE("Unknown constant pointer!"); + llvm_unreachable("Unknown constant pointer!"); } return 0; } @@ -854,10 +854,10 @@ unsigned Andersens::getNodeForConstantPointerTarget(Constant *C) { return getNodeForConstantPointerTarget(CE->getOperand(0)); default: cerr << "Constant Expr not yet handled: " << *CE << "\n"; - llvm_unreachable(); + llvm_unreachable(0); } } else { - LLVM_UNREACHABLE("Unknown constant pointer!"); + llvm_unreachable("Unknown constant pointer!"); } return 0; } @@ -1154,7 +1154,7 @@ void Andersens::visitInstruction(Instruction &I) { default: // Is this something we aren't handling yet? cerr << "Unknown instruction: " << I; - llvm_unreachable(); + llvm_unreachable(0); } } @@ -1244,7 +1244,7 @@ void Andersens::visitSelectInst(SelectInst &SI) { } void Andersens::visitVAArg(VAArgInst &I) { - LLVM_UNREACHABLE("vaarg not handled yet!"); + llvm_unreachable("vaarg not handled yet!"); } /// AddConstraintsForCall - Add constraints for a call with actual arguments diff --git a/lib/Analysis/InstCount.cpp b/lib/Analysis/InstCount.cpp index 2dbf0d4..c5a65f0 100644 --- a/lib/Analysis/InstCount.cpp +++ b/lib/Analysis/InstCount.cpp @@ -48,7 +48,7 @@ namespace { void visitInstruction(Instruction &I) { cerr << "Instruction Count does not know about " << I; - llvm_unreachable(); + llvm_unreachable(0); } public: static char ID; // Pass identification, replacement for typeid diff --git a/lib/Analysis/LoopDependenceAnalysis.cpp b/lib/Analysis/LoopDependenceAnalysis.cpp index 79f92a6..156642a 100644 --- a/lib/Analysis/LoopDependenceAnalysis.cpp +++ b/lib/Analysis/LoopDependenceAnalysis.cpp @@ -64,7 +64,7 @@ static Value *GetPointerOperand(Value *I) { return i->getPointerOperand(); if (StoreInst *i = dyn_cast<StoreInst>(I)) return i->getPointerOperand(); - LLVM_UNREACHABLE("Value is no load or store instruction!"); + llvm_unreachable("Value is no load or store instruction!"); // Never reached. return 0; } diff --git a/lib/Analysis/ScalarEvolution.cpp b/lib/Analysis/ScalarEvolution.cpp index 2b4623c..0c17f14 100644 --- a/lib/Analysis/ScalarEvolution.cpp +++ b/lib/Analysis/ScalarEvolution.cpp @@ -148,17 +148,17 @@ SCEVCouldNotCompute::SCEVCouldNotCompute() : SCEV(FoldingSetNodeID(), scCouldNotCompute) {} bool SCEVCouldNotCompute::isLoopInvariant(const Loop *L) const { - LLVM_UNREACHABLE("Attempt to use a SCEVCouldNotCompute object!"); + llvm_unreachable("Attempt to use a SCEVCouldNotCompute object!"); return false; } const Type *SCEVCouldNotCompute::getType() const { - LLVM_UNREACHABLE("Attempt to use a SCEVCouldNotCompute object!"); + llvm_unreachable("Attempt to use a SCEVCouldNotCompute object!"); return 0; } bool SCEVCouldNotCompute::hasComputableLoopEvolution(const Loop *L) const { - LLVM_UNREACHABLE("Attempt to use a SCEVCouldNotCompute object!"); + llvm_unreachable("Attempt to use a SCEVCouldNotCompute object!"); return false; } @@ -285,7 +285,7 @@ SCEVCommutativeExpr::replaceSymbolicValuesWithConcrete( else if (isa<SCEVUMaxExpr>(this)) return SE.getUMaxExpr(NewOps); else - LLVM_UNREACHABLE("Unknown commutative expr!"); + llvm_unreachable("Unknown commutative expr!"); } } return this; @@ -506,7 +506,7 @@ namespace { return operator()(LC->getOperand(), RC->getOperand()); } - LLVM_UNREACHABLE("Unknown SCEV kind!"); + llvm_unreachable("Unknown SCEV kind!"); return false; } }; @@ -3475,7 +3475,7 @@ GetAddressedElementFromGlobal(LLVMContext *Context, GlobalVariable *GV, if (Idx >= ATy->getNumElements()) return 0; // Bogus program Init = Context->getNullValue(ATy->getElementType()); } else { - LLVM_UNREACHABLE("Unknown constant aggregate type!"); + llvm_unreachable("Unknown constant aggregate type!"); } return 0; } else { @@ -3885,7 +3885,7 @@ const SCEV *ScalarEvolution::getSCEVAtScope(const SCEV *V, const Loop *L) { return getSMaxExpr(NewOps); if (isa<SCEVUMaxExpr>(Comm)) return getUMaxExpr(NewOps); - LLVM_UNREACHABLE("Unknown commutative SCEV type!"); + llvm_unreachable("Unknown commutative SCEV type!"); } } // If we got here, all operands are loop invariant. @@ -3936,7 +3936,7 @@ const SCEV *ScalarEvolution::getSCEVAtScope(const SCEV *V, const Loop *L) { return getTruncateExpr(Op, Cast->getType()); } - LLVM_UNREACHABLE("Unknown SCEV type!"); + llvm_unreachable("Unknown SCEV type!"); return 0; } diff --git a/lib/AsmParser/LLLexer.cpp b/lib/AsmParser/LLLexer.cpp index c854031..97e8e6a 100644 --- a/lib/AsmParser/LLLexer.cpp +++ b/lib/AsmParser/LLLexer.cpp @@ -700,7 +700,7 @@ lltok::Kind LLLexer::Lex0x() { uint64_t Pair[2]; switch (Kind) { - default: LLVM_UNREACHABLE("Unknown kind!"); + default: llvm_unreachable("Unknown kind!"); case 'K': // F80HexFPConstant - x87 long double in hexadecimal format (10 bytes) FP80HexToIntPair(TokStart+3, CurPtr, Pair); diff --git a/lib/AsmParser/LLParser.cpp b/lib/AsmParser/LLParser.cpp index fca2460..080575d 100644 --- a/lib/AsmParser/LLParser.cpp +++ b/lib/AsmParser/LLParser.cpp @@ -2041,7 +2041,7 @@ bool LLParser::ConvertGlobalValIDToValue(const Type *Ty, ValID &ID, return Error(ID.Loc, "functions are not values, refer to them as pointers"); switch (ID.Kind) { - default: LLVM_UNREACHABLE("Unknown ValID!"); + default: llvm_unreachable("Unknown ValID!"); case ValID::t_LocalID: case ValID::t_LocalName: return Error(ID.Loc, "invalid use of function-local name"); @@ -2836,7 +2836,7 @@ bool LLParser::ParseArithmetic(Instruction *&Inst, PerFunctionState &PFS, bool Valid; switch (OperandType) { - default: LLVM_UNREACHABLE("Unknown operand type!"); + default: llvm_unreachable("Unknown operand type!"); case 0: // int or FP. Valid = LHS->getType()->isIntOrIntVector() || LHS->getType()->isFPOrFPVector(); diff --git a/lib/Bitcode/Writer/BitcodeWriter.cpp b/lib/Bitcode/Writer/BitcodeWriter.cpp index 18f3262..55ec9e5 100644 --- a/lib/Bitcode/Writer/BitcodeWriter.cpp +++ b/lib/Bitcode/Writer/BitcodeWriter.cpp @@ -59,7 +59,7 @@ enum { static unsigned GetEncodedCastOpcode(unsigned Opcode) { switch (Opcode) { - default: LLVM_UNREACHABLE("Unknown cast instruction!"); + default: llvm_unreachable("Unknown cast instruction!"); case Instruction::Trunc : return bitc::CAST_TRUNC; case Instruction::ZExt : return bitc::CAST_ZEXT; case Instruction::SExt : return bitc::CAST_SEXT; @@ -77,7 +77,7 @@ static unsigned GetEncodedCastOpcode(unsigned Opcode) { static unsigned GetEncodedBinaryOpcode(unsigned Opcode) { switch (Opcode) { - default: LLVM_UNREACHABLE("Unknown binary instruction!"); + default: llvm_unreachable("Unknown binary instruction!"); case Instruction::Add: case Instruction::FAdd: return bitc::BINOP_ADD; case Instruction::Sub: @@ -201,7 +201,7 @@ static void WriteTypeTable(const ValueEnumerator &VE, BitstreamWriter &Stream) { unsigned Code = 0; switch (T->getTypeID()) { - default: LLVM_UNREACHABLE("Unknown type!"); + default: llvm_unreachable("Unknown type!"); case Type::VoidTyID: Code = bitc::TYPE_CODE_VOID; break; case Type::FloatTyID: Code = bitc::TYPE_CODE_FLOAT; break; case Type::DoubleTyID: Code = bitc::TYPE_CODE_DOUBLE; break; @@ -279,7 +279,7 @@ static void WriteTypeTable(const ValueEnumerator &VE, BitstreamWriter &Stream) { static unsigned getEncodedLinkage(const GlobalValue *GV) { switch (GV->getLinkage()) { - default: LLVM_UNREACHABLE("Invalid linkage!"); + default: llvm_unreachable("Invalid linkage!"); case GlobalValue::GhostLinkage: // Map ghost linkage onto external. case GlobalValue::ExternalLinkage: return 0; case GlobalValue::WeakAnyLinkage: return 1; @@ -299,7 +299,7 @@ static unsigned getEncodedLinkage(const GlobalValue *GV) { static unsigned getEncodedVisibility(const GlobalValue *GV) { switch (GV->getVisibility()) { - default: LLVM_UNREACHABLE("Invalid visibility!"); + default: llvm_unreachable("Invalid visibility!"); case GlobalValue::DefaultVisibility: return 0; case GlobalValue::HiddenVisibility: return 1; case GlobalValue::ProtectedVisibility: return 2; @@ -713,7 +713,7 @@ static void WriteConstants(unsigned FirstVal, unsigned LastVal, } } } else { - LLVM_UNREACHABLE("Unknown constant!"); + llvm_unreachable("Unknown constant!"); } Stream.EmitRecord(Code, Record, AbbrevToUse); Record.clear(); @@ -1127,7 +1127,7 @@ static void WriteBlockInfo(const ValueEnumerator &VE, BitstreamWriter &Stream) { Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 8)); if (Stream.EmitBlockInfoAbbrev(bitc::VALUE_SYMTAB_BLOCK_ID, Abbv) != VST_ENTRY_8_ABBREV) - LLVM_UNREACHABLE("Unexpected abbrev ordering!"); + llvm_unreachable("Unexpected abbrev ordering!"); } { // 7-bit fixed width VST_ENTRY strings. @@ -1138,7 +1138,7 @@ static void WriteBlockInfo(const ValueEnumerator &VE, BitstreamWriter &Stream) { Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 7)); if (Stream.EmitBlockInfoAbbrev(bitc::VALUE_SYMTAB_BLOCK_ID, Abbv) != VST_ENTRY_7_ABBREV) - LLVM_UNREACHABLE("Unexpected abbrev ordering!"); + llvm_unreachable("Unexpected abbrev ordering!"); } { // 6-bit char6 VST_ENTRY strings. BitCodeAbbrev *Abbv = new BitCodeAbbrev(); @@ -1148,7 +1148,7 @@ static void WriteBlockInfo(const ValueEnumerator &VE, BitstreamWriter &Stream) { Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Char6)); if (Stream.EmitBlockInfoAbbrev(bitc::VALUE_SYMTAB_BLOCK_ID, Abbv) != VST_ENTRY_6_ABBREV) - LLVM_UNREACHABLE("Unexpected abbrev ordering!"); + llvm_unreachable("Unexpected abbrev ordering!"); } { // 6-bit char6 VST_BBENTRY strings. BitCodeAbbrev *Abbv = new BitCodeAbbrev(); @@ -1158,7 +1158,7 @@ static void WriteBlockInfo(const ValueEnumerator &VE, BitstreamWriter &Stream) { Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Char6)); if (Stream.EmitBlockInfoAbbrev(bitc::VALUE_SYMTAB_BLOCK_ID, Abbv) != VST_BBENTRY_6_ABBREV) - LLVM_UNREACHABLE("Unexpected abbrev ordering!"); + llvm_unreachable("Unexpected abbrev ordering!"); } @@ -1170,7 +1170,7 @@ static void WriteBlockInfo(const ValueEnumerator &VE, BitstreamWriter &Stream) { Log2_32_Ceil(VE.getTypes().size()+1))); if (Stream.EmitBlockInfoAbbrev(bitc::CONSTANTS_BLOCK_ID, Abbv) != CONSTANTS_SETTYPE_ABBREV) - LLVM_UNREACHABLE("Unexpected abbrev ordering!"); + llvm_unreachable("Unexpected abbrev ordering!"); } { // INTEGER abbrev for CONSTANTS_BLOCK. @@ -1179,7 +1179,7 @@ static void WriteBlockInfo(const ValueEnumerator &VE, BitstreamWriter &Stream) { Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 8)); if (Stream.EmitBlockInfoAbbrev(bitc::CONSTANTS_BLOCK_ID, Abbv) != CONSTANTS_INTEGER_ABBREV) - LLVM_UNREACHABLE("Unexpected abbrev ordering!"); + llvm_unreachable("Unexpected abbrev ordering!"); } { // CE_CAST abbrev for CONSTANTS_BLOCK. @@ -1192,14 +1192,14 @@ static void WriteBlockInfo(const ValueEnumerator &VE, BitstreamWriter &Stream) { if (Stream.EmitBlockInfoAbbrev(bitc::CONSTANTS_BLOCK_ID, Abbv) != CONSTANTS_CE_CAST_Abbrev) - LLVM_UNREACHABLE("Unexpected abbrev ordering!"); + llvm_unreachable("Unexpected abbrev ordering!"); } { // NULL abbrev for CONSTANTS_BLOCK. BitCodeAbbrev *Abbv = new BitCodeAbbrev(); Abbv->Add(BitCodeAbbrevOp(bitc::CST_CODE_NULL)); if (Stream.EmitBlockInfoAbbrev(bitc::CONSTANTS_BLOCK_ID, Abbv) != CONSTANTS_NULL_Abbrev) - LLVM_UNREACHABLE("Unexpected abbrev ordering!"); + llvm_unreachable("Unexpected abbrev ordering!"); } // FIXME: This should only use space for first class types! @@ -1212,7 +1212,7 @@ static void WriteBlockInfo(const ValueEnumerator &VE, BitstreamWriter &Stream) { Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 1)); // volatile if (Stream.EmitBlockInfoAbbrev(bitc::FUNCTION_BLOCK_ID, Abbv) != FUNCTION_INST_LOAD_ABBREV) - LLVM_UNREACHABLE("Unexpected abbrev ordering!"); + llvm_unreachable("Unexpected abbrev ordering!"); } { // INST_BINOP abbrev for FUNCTION_BLOCK. BitCodeAbbrev *Abbv = new BitCodeAbbrev(); @@ -1222,7 +1222,7 @@ static void WriteBlockInfo(const ValueEnumerator &VE, BitstreamWriter &Stream) { Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 4)); // opc if (Stream.EmitBlockInfoAbbrev(bitc::FUNCTION_BLOCK_ID, Abbv) != FUNCTION_INST_BINOP_ABBREV) - LLVM_UNREACHABLE("Unexpected abbrev ordering!"); + llvm_unreachable("Unexpected abbrev ordering!"); } { // INST_CAST abbrev for FUNCTION_BLOCK. BitCodeAbbrev *Abbv = new BitCodeAbbrev(); @@ -1233,7 +1233,7 @@ static void WriteBlockInfo(const ValueEnumerator &VE, BitstreamWriter &Stream) { Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 4)); // opc if (Stream.EmitBlockInfoAbbrev(bitc::FUNCTION_BLOCK_ID, Abbv) != FUNCTION_INST_CAST_ABBREV) - LLVM_UNREACHABLE("Unexpected abbrev ordering!"); + llvm_unreachable("Unexpected abbrev ordering!"); } { // INST_RET abbrev for FUNCTION_BLOCK. @@ -1241,7 +1241,7 @@ static void WriteBlockInfo(const ValueEnumerator &VE, BitstreamWriter &Stream) { Abbv->Add(BitCodeAbbrevOp(bitc::FUNC_CODE_INST_RET)); if (Stream.EmitBlockInfoAbbrev(bitc::FUNCTION_BLOCK_ID, Abbv) != FUNCTION_INST_RET_VOID_ABBREV) - LLVM_UNREACHABLE("Unexpected abbrev ordering!"); + llvm_unreachable("Unexpected abbrev ordering!"); } { // INST_RET abbrev for FUNCTION_BLOCK. BitCodeAbbrev *Abbv = new BitCodeAbbrev(); @@ -1249,14 +1249,14 @@ static void WriteBlockInfo(const ValueEnumerator &VE, BitstreamWriter &Stream) { Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // ValID if (Stream.EmitBlockInfoAbbrev(bitc::FUNCTION_BLOCK_ID, Abbv) != FUNCTION_INST_RET_VAL_ABBREV) - LLVM_UNREACHABLE("Unexpected abbrev ordering!"); + llvm_unreachable("Unexpected abbrev ordering!"); } { // INST_UNREACHABLE abbrev for FUNCTION_BLOCK. BitCodeAbbrev *Abbv = new BitCodeAbbrev(); Abbv->Add(BitCodeAbbrevOp(bitc::FUNC_CODE_INST_UNREACHABLE)); if (Stream.EmitBlockInfoAbbrev(bitc::FUNCTION_BLOCK_ID, Abbv) != FUNCTION_INST_UNREACHABLE_ABBREV) - LLVM_UNREACHABLE("Unexpected abbrev ordering!"); + llvm_unreachable("Unexpected abbrev ordering!"); } Stream.ExitBlock(); diff --git a/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/lib/CodeGen/AsmPrinter/AsmPrinter.cpp index 867b003..d0b0aab 100644 --- a/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ b/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -238,7 +238,7 @@ bool AsmPrinter::doFinalization(Module &M) { else if (I->hasWeakLinkage()) O << TAI->getWeakRefDirective() << Name << '\n'; else if (!I->hasLocalLinkage()) - LLVM_UNREACHABLE("Invalid alias linkage"); + llvm_unreachable("Invalid alias linkage"); printVisibility(Name, I->getVisibility()); @@ -902,7 +902,7 @@ void AsmPrinter::EmitConstantValueOnly(const Constant *CV) { case Instruction::SIToFP: case Instruction::FPToUI: case Instruction::FPToSI: - LLVM_UNREACHABLE("FIXME: Don't yet support this kind of constant cast expr"); + llvm_unreachable("FIXME: Don't yet support this kind of constant cast expr"); break; case Instruction::BitCast: return EmitConstantValueOnly(CE->getOperand(0)); @@ -968,10 +968,10 @@ void AsmPrinter::EmitConstantValueOnly(const Constant *CV) { O << ')'; break; default: - LLVM_UNREACHABLE("Unsupported operator!"); + llvm_unreachable("Unsupported operator!"); } } else { - LLVM_UNREACHABLE("Unknown constant value!"); + llvm_unreachable("Unknown constant value!"); } } @@ -1210,7 +1210,7 @@ void AsmPrinter::EmitGlobalConstantFP(const ConstantFP *CFP, O << '\n'; } return; - } else LLVM_UNREACHABLE("Floating point constant type not handled"); + } else llvm_unreachable("Floating point constant type not handled"); } void AsmPrinter::EmitGlobalConstantLargeInt(const ConstantInt *CI, @@ -1302,7 +1302,7 @@ void AsmPrinter::EmitGlobalConstant(const Constant *CV, unsigned AddrSpace) { void AsmPrinter::EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) { // Target doesn't support this yet! - LLVM_UNREACHABLE("Target does not support EmitMachineConstantPoolValue"); + llvm_unreachable("Target does not support EmitMachineConstantPoolValue"); } /// PrintSpecial - Print information related to the specified machine instr @@ -1661,7 +1661,7 @@ void AsmPrinter::printDataDirective(const Type *type, unsigned AddrSpace) { "Target cannot handle 64-bit constant exprs!"); O << TAI->getData64bitsDirective(AddrSpace); } else { - LLVM_UNREACHABLE("Target cannot handle given data directive width!"); + llvm_unreachable("Target cannot handle given data directive width!"); } break; } @@ -1747,7 +1747,7 @@ GCMetadataPrinter *AsmPrinter::GetOrCreateGCPrinter(GCStrategy *S) { } cerr << "no GCMetadataPrinter registered for GC: " << Name << "\n"; - llvm_unreachable(); + llvm_unreachable(0); } /// EmitComments - Pretty-print comments for instructions diff --git a/lib/CodeGen/AsmPrinter/DIE.cpp b/lib/CodeGen/AsmPrinter/DIE.cpp index dd61ca3..a35ee28 100644 --- a/lib/CodeGen/AsmPrinter/DIE.cpp +++ b/lib/CodeGen/AsmPrinter/DIE.cpp @@ -207,7 +207,7 @@ void DIEInteger::EmitValue(Dwarf *D, unsigned Form) const { case dwarf::DW_FORM_data8: Asm->EmitInt64(Integer); break; case dwarf::DW_FORM_udata: Asm->EmitULEB128Bytes(Integer); break; case dwarf::DW_FORM_sdata: Asm->EmitSLEB128Bytes(Integer); break; - default: LLVM_UNREACHABLE("DIE Value form not supported yet"); + default: llvm_unreachable("DIE Value form not supported yet"); } } @@ -226,7 +226,7 @@ unsigned DIEInteger::SizeOf(const TargetData *TD, unsigned Form) const { case dwarf::DW_FORM_data8: return sizeof(int64_t); case dwarf::DW_FORM_udata: return TargetAsmInfo::getULEB128Size(Integer); case dwarf::DW_FORM_sdata: return TargetAsmInfo::getSLEB128Size(Integer); - default: LLVM_UNREACHABLE("DIE Value form not supported yet"); break; + default: llvm_unreachable("DIE Value form not supported yet"); break; } return 0; } @@ -482,7 +482,7 @@ void DIEBlock::EmitValue(Dwarf *D, unsigned Form) const { case dwarf::DW_FORM_block2: Asm->EmitInt16(Size); break; case dwarf::DW_FORM_block4: Asm->EmitInt32(Size); break; case dwarf::DW_FORM_block: Asm->EmitULEB128Bytes(Size); break; - default: LLVM_UNREACHABLE("Improper form for block"); break; + default: llvm_unreachable("Improper form for block"); break; } const SmallVector<DIEAbbrevData, 8> &AbbrevData = Abbrev.getData(); @@ -500,7 +500,7 @@ unsigned DIEBlock::SizeOf(const TargetData *TD, unsigned Form) const { case dwarf::DW_FORM_block2: return Size + sizeof(int16_t); case dwarf::DW_FORM_block4: return Size + sizeof(int32_t); case dwarf::DW_FORM_block: return Size + TargetAsmInfo::getULEB128Size(Size); - default: LLVM_UNREACHABLE("Improper form for block"); break; + default: llvm_unreachable("Improper form for block"); break; } return 0; } diff --git a/lib/CodeGen/AsmPrinter/DwarfPrinter.cpp b/lib/CodeGen/AsmPrinter/DwarfPrinter.cpp index be274ca..955c073 100644 --- a/lib/CodeGen/AsmPrinter/DwarfPrinter.cpp +++ b/lib/CodeGen/AsmPrinter/DwarfPrinter.cpp @@ -191,7 +191,7 @@ void Dwarf::EmitFrameMoves(const char *BaseLabel, unsigned BaseLabelID, Asm->EmitULEB128Bytes(Offset); Asm->EOL("Offset"); } else { - LLVM_UNREACHABLE("Machine move not supported yet."); + llvm_unreachable("Machine move not supported yet."); } } else if (Src.isReg() && Src.getReg() == MachineLocation::VirtualFP) { @@ -201,7 +201,7 @@ void Dwarf::EmitFrameMoves(const char *BaseLabel, unsigned BaseLabelID, Asm->EmitULEB128Bytes(RI->getDwarfRegNum(Dst.getReg(), isEH)); Asm->EOL("Register"); } else { - LLVM_UNREACHABLE("Machine move not supported yet."); + llvm_unreachable("Machine move not supported yet."); } } else { unsigned Reg = RI->getDwarfRegNum(Src.getReg(), isEH); diff --git a/lib/CodeGen/BranchFolding.cpp b/lib/CodeGen/BranchFolding.cpp index c839b3e..193bbb6 100644 --- a/lib/CodeGen/BranchFolding.cpp +++ b/lib/CodeGen/BranchFolding.cpp @@ -462,7 +462,7 @@ static bool MergeCompare(const std::pair<unsigned,MachineBasicBlock*> &p, // _GLIBCXX_DEBUG checks strict weak ordering, which involves comparing // an object with itself. #ifndef _GLIBCXX_DEBUG - LLVM_UNREACHABLE("Predecessor appears twice"); + llvm_unreachable("Predecessor appears twice"); #endif return false; } diff --git a/lib/CodeGen/ELFCodeEmitter.cpp b/lib/CodeGen/ELFCodeEmitter.cpp index 57dc41f..5133e74 100644 --- a/lib/CodeGen/ELFCodeEmitter.cpp +++ b/lib/CodeGen/ELFCodeEmitter.cpp @@ -108,7 +108,7 @@ bool ELFCodeEmitter::finishFunction(MachineFunction &MF) { MR.setResultPointer((void*)Addr); MR.setConstantVal(JumpTableSectionIdx); } else { - LLVM_UNREACHABLE("Unhandled relocation type"); + llvm_unreachable("Unhandled relocation type"); } ES->addRelocation(MR); } diff --git a/lib/CodeGen/ELFWriter.cpp b/lib/CodeGen/ELFWriter.cpp index a26f93b..e041bd3 100644 --- a/lib/CodeGen/ELFWriter.cpp +++ b/lib/CodeGen/ELFWriter.cpp @@ -149,7 +149,7 @@ bool ELFWriter::doInitialization(Module &M) { unsigned ELFWriter::getGlobalELFVisibility(const GlobalValue *GV) { switch (GV->getVisibility()) { default: - LLVM_UNREACHABLE("unknown visibility type"); + llvm_unreachable("unknown visibility type"); case GlobalValue::DefaultVisibility: return ELFSym::STV_DEFAULT; case GlobalValue::HiddenVisibility: @@ -359,9 +359,9 @@ void ELFWriter::EmitGlobalConstant(const Constant *CV, ELFSection &GblS) { else if (CFP->getType() == Type::FloatTy) GblS.emitWord32(Val); else if (CFP->getType() == Type::X86_FP80Ty) { - LLVM_UNREACHABLE("X86_FP80Ty global emission not implemented"); + llvm_unreachable("X86_FP80Ty global emission not implemented"); } else if (CFP->getType() == Type::PPC_FP128Ty) - LLVM_UNREACHABLE("PPC_FP128Ty global emission not implemented"); + llvm_unreachable("PPC_FP128Ty global emission not implemented"); return; } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) { if (Size == 4) @@ -369,7 +369,7 @@ void ELFWriter::EmitGlobalConstant(const Constant *CV, ELFSection &GblS) { else if (Size == 8) GblS.emitWord64(CI->getZExtValue()); else - LLVM_UNREACHABLE("LargeInt global emission not implemented"); + llvm_unreachable("LargeInt global emission not implemented"); return; } else if (const ConstantVector *CP = dyn_cast<ConstantVector>(CV)) { const VectorType *PTy = CP->getType(); @@ -377,7 +377,7 @@ void ELFWriter::EmitGlobalConstant(const Constant *CV, ELFSection &GblS) { EmitGlobalConstant(CP->getOperand(I), GblS); return; } - LLVM_UNREACHABLE("unknown global constant"); + llvm_unreachable("unknown global constant"); } diff --git a/lib/CodeGen/GCMetadata.cpp b/lib/CodeGen/GCMetadata.cpp index f711157..15d9a05 100644 --- a/lib/CodeGen/GCMetadata.cpp +++ b/lib/CodeGen/GCMetadata.cpp @@ -95,7 +95,7 @@ GCStrategy *GCModuleInfo::getOrCreateStrategy(const Module *M, } cerr << "unsupported GC: " << Name << "\n"; - llvm_unreachable(); + llvm_unreachable(0); } GCFunctionInfo &GCModuleInfo::getFunctionInfo(const Function &F) { @@ -144,7 +144,7 @@ void Printer::getAnalysisUsage(AnalysisUsage &AU) const { static const char *DescKind(GC::PointKind Kind) { switch (Kind) { - default: LLVM_UNREACHABLE("Unknown GC point kind"); + default: llvm_unreachable("Unknown GC point kind"); case GC::Loop: return "loop"; case GC::Return: return "return"; case GC::PreCall: return "pre-call"; diff --git a/lib/CodeGen/GCStrategy.cpp b/lib/CodeGen/GCStrategy.cpp index 560cf7d..af5abad 100644 --- a/lib/CodeGen/GCStrategy.cpp +++ b/lib/CodeGen/GCStrategy.cpp @@ -109,7 +109,7 @@ bool GCStrategy::initializeCustomLowering(Module &M) { return false; } bool GCStrategy::performCustomLowering(Function &F) { cerr << "gc " << getName() << " must override performCustomLowering.\n"; - llvm_unreachable(); + llvm_unreachable(0); return 0; } diff --git a/lib/CodeGen/IfConversion.cpp b/lib/CodeGen/IfConversion.cpp index 02249c9..608d18d 100644 --- a/lib/CodeGen/IfConversion.cpp +++ b/lib/CodeGen/IfConversion.cpp @@ -1135,7 +1135,7 @@ void IfConverter::PredicateBlock(BBInfo &BBI, #ifndef NDEBUG cerr << "Unable to predicate " << *I << "!\n"; #endif - llvm_unreachable(); + llvm_unreachable(0); } } @@ -1171,7 +1171,7 @@ void IfConverter::CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI, #ifndef NDEBUG cerr << "Unable to predicate " << *I << "!\n"; #endif - llvm_unreachable(); + llvm_unreachable(0); } } diff --git a/lib/CodeGen/IntrinsicLowering.cpp b/lib/CodeGen/IntrinsicLowering.cpp index 270a232..6ec3a62 100644 --- a/lib/CodeGen/IntrinsicLowering.cpp +++ b/lib/CodeGen/IntrinsicLowering.cpp @@ -157,7 +157,7 @@ static Value *LowerBSWAP(Value *V, Instruction *IP) { IRBuilder<> Builder(IP->getParent(), IP); switch(BitSize) { - default: LLVM_UNREACHABLE("Unhandled type size of value to byteswap!"); + default: llvm_unreachable("Unhandled type size of value to byteswap!"); case 16: { Value *Tmp1 = Builder.CreateShl(V, ConstantInt::get(V->getType(), 8), "bswap.2"); @@ -295,7 +295,7 @@ static void ReplaceFPIntrinsicWithCall(CallInst *CI, const char *Fname, const char *Dname, const char *LDname) { switch (CI->getOperand(1)->getType()->getTypeID()) { - default: LLVM_UNREACHABLE("Invalid type in intrinsic"); + default: llvm_unreachable("Invalid type in intrinsic"); case Type::FloatTyID: ReplaceCallWith(Fname, CI, CI->op_begin() + 1, CI->op_end(), Type::FloatTy); diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp index ed23bef..3887fc8 100644 --- a/lib/CodeGen/LiveIntervalAnalysis.cpp +++ b/lib/CodeGen/LiveIntervalAnalysis.cpp @@ -1102,7 +1102,7 @@ unsigned LiveIntervals::getVNInfoSourceReg(const VNInfo *VNI) const { unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; if (tii_->isMoveInstr(*VNI->copy, SrcReg, DstReg, SrcSubReg, DstSubReg)) return SrcReg; - LLVM_UNREACHABLE("Unrecognized copy instruction!"); + llvm_unreachable("Unrecognized copy instruction!"); return 0; } diff --git a/lib/CodeGen/MachOCodeEmitter.cpp b/lib/CodeGen/MachOCodeEmitter.cpp index a076a3c..14ebc3f 100644 --- a/lib/CodeGen/MachOCodeEmitter.cpp +++ b/lib/CodeGen/MachOCodeEmitter.cpp @@ -105,7 +105,7 @@ bool MachOCodeEmitter::finishFunction(MachineFunction &MF) { // FIXME: This should be a set or something that uniques MOW.PendingGlobals.push_back(MR.getGlobalValue()); } else { - LLVM_UNREACHABLE("Unhandled relocation type"); + llvm_unreachable("Unhandled relocation type"); } MOS->addRelocation(MR); } diff --git a/lib/CodeGen/MachOWriter.cpp b/lib/CodeGen/MachOWriter.cpp index 7542d9e..5cbe6fd 100644 --- a/lib/CodeGen/MachOWriter.cpp +++ b/lib/CodeGen/MachOWriter.cpp @@ -635,7 +635,7 @@ void MachOWriter::InitMem(const Constant *C, uintptr_t Offset, case Instruction::Add: default: cerr << "ConstantExpr not handled as global var init: " << *CE << "\n"; - llvm_unreachable(); + llvm_unreachable(0); } } else if (PC->getType()->isSingleValueType()) { unsigned char *ptr = (unsigned char *)PA; @@ -669,7 +669,7 @@ void MachOWriter::InitMem(const Constant *C, uintptr_t Offset, ptr[6] = val >> 48; ptr[7] = val >> 56; } else { - LLVM_UNREACHABLE("Not implemented: bit widths > 64"); + llvm_unreachable("Not implemented: bit widths > 64"); } break; } @@ -710,7 +710,7 @@ void MachOWriter::InitMem(const Constant *C, uintptr_t Offset, ScatteredOffset)); ScatteredOffset = 0; } else - LLVM_UNREACHABLE("Unknown constant pointer type!"); + llvm_unreachable("Unknown constant pointer type!"); break; default: std::string msg; @@ -733,7 +733,7 @@ void MachOWriter::InitMem(const Constant *C, uintptr_t Offset, PA+SL->getElementOffset(i))); } else { cerr << "Bad Type: " << *PC->getType() << "\n"; - LLVM_UNREACHABLE("Unknown constant type to initialize memory with!"); + llvm_unreachable("Unknown constant type to initialize memory with!"); } } } @@ -749,7 +749,7 @@ MachOSym::MachOSym(const GlobalValue *gv, std::string name, uint8_t sect, switch (GV->getLinkage()) { default: - LLVM_UNREACHABLE("Unexpected linkage type!"); + llvm_unreachable("Unexpected linkage type!"); break; case GlobalValue::WeakAnyLinkage: case GlobalValue::WeakODRLinkage: diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp index 2435855..98cc767 100644 --- a/lib/CodeGen/MachineInstr.cpp +++ b/lib/CodeGen/MachineInstr.cpp @@ -157,7 +157,7 @@ bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const { return false; switch (getType()) { - default: LLVM_UNREACHABLE("Unrecognized operand type"); + default: llvm_unreachable("Unrecognized operand type"); case MachineOperand::MO_Register: return getReg() == Other.getReg() && isDef() == Other.isDef() && getSubReg() == Other.getSubReg(); @@ -275,7 +275,7 @@ void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const { OS << '>'; break; default: - LLVM_UNREACHABLE("Unrecognized operand type"); + llvm_unreachable("Unrecognized operand type"); } if (unsigned TF = getTargetFlags()) diff --git a/lib/CodeGen/MachineModuleInfo.cpp b/lib/CodeGen/MachineModuleInfo.cpp index 798492b..f5d92f1 100644 --- a/lib/CodeGen/MachineModuleInfo.cpp +++ b/lib/CodeGen/MachineModuleInfo.cpp @@ -291,7 +291,7 @@ unsigned MachineModuleInfo::getPersonalityIndex() const { } // This should never happen - LLVM_UNREACHABLE("Personality function should be set!"); + llvm_unreachable("Personality function should be set!"); return 0; } diff --git a/lib/CodeGen/PostRASchedulerList.cpp b/lib/CodeGen/PostRASchedulerList.cpp index 77cbf29..c02647a 100644 --- a/lib/CodeGen/PostRASchedulerList.cpp +++ b/lib/CodeGen/PostRASchedulerList.cpp @@ -794,7 +794,7 @@ void SchedulePostRATDList::ReleaseSucc(SUnit *SU, SDep *SuccEdge) { cerr << "*** Scheduling failed! ***\n"; SuccSU->dump(this); cerr << " has been released too many times!\n"; - llvm_unreachable(); + llvm_unreachable(0); } #endif diff --git a/lib/CodeGen/PseudoSourceValue.cpp b/lib/CodeGen/PseudoSourceValue.cpp index 55a6cf5..81cbfb8 100644 --- a/lib/CodeGen/PseudoSourceValue.cpp +++ b/lib/CodeGen/PseudoSourceValue.cpp @@ -84,7 +84,7 @@ bool PseudoSourceValue::isConstant(const MachineFrameInfo *) const { this == getConstantPool() || this == getJumpTable()) return true; - LLVM_UNREACHABLE("Unknown PseudoSourceValue!"); + llvm_unreachable("Unknown PseudoSourceValue!"); return false; } diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp index abbec1a..63a99e4 100644 --- a/lib/CodeGen/RegAllocLinearScan.cpp +++ b/lib/CodeGen/RegAllocLinearScan.cpp @@ -237,7 +237,7 @@ namespace { } } if (Error) - llvm_unreachable(); + llvm_unreachable(0); #endif regUse_.clear(); regUseBackUp_.clear(); diff --git a/lib/CodeGen/SelectionDAG/CallingConvLower.cpp b/lib/CodeGen/SelectionDAG/CallingConvLower.cpp index 9289711..2f4db28 100644 --- a/lib/CodeGen/SelectionDAG/CallingConvLower.cpp +++ b/lib/CodeGen/SelectionDAG/CallingConvLower.cpp @@ -67,11 +67,11 @@ void CCState::AnalyzeFormalArguments(SDNode *TheArgs, CCAssignFn Fn) { ISD::ArgFlagsTy ArgFlags = cast<ARG_FLAGSSDNode>(TheArgs->getOperand(3+i))->getArgFlags(); if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) { - std::string msg; - raw_string_ostream Msg(msg); - Msg << "Formal argument #" << i << " has unhandled type " +#ifndef NDEBUG + cerr << "Formal argument #" << i << " has unhandled type " << ArgVT.getMVTString(); - llvm_report_error(Msg.str()); +#endif + llvm_unreachable(0); } } } @@ -84,12 +84,12 @@ void CCState::AnalyzeReturn(SDNode *TheRet, CCAssignFn Fn) { MVT VT = TheRet->getOperand(i*2+1).getValueType(); ISD::ArgFlagsTy ArgFlags = cast<ARG_FLAGSSDNode>(TheRet->getOperand(i*2+2))->getArgFlags(); - if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)){ - std::string msg; - raw_string_ostream Msg(msg); - Msg << "Return operand #" << i << " has unhandled type " + if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) { +#ifndef NDEBUG + cerr << "Return operand #" << i << " has unhandled type " << VT.getMVTString(); - llvm_report_error(Msg.str()); +#endif + llvm_unreachable(0); } } } @@ -103,11 +103,11 @@ void CCState::AnalyzeCallOperands(CallSDNode *TheCall, CCAssignFn Fn) { MVT ArgVT = TheCall->getArg(i).getValueType(); ISD::ArgFlagsTy ArgFlags = TheCall->getArgFlags(i); if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) { - std::string msg; - raw_string_ostream Msg(msg); - Msg << "Call operand #" << i << " has unhandled type " +#ifndef NDEBUG + cerr << "Call operand #" << i << " has unhandled type " << ArgVT.getMVTString(); - llvm_report_error(Msg.str()); +#endif + llvm_unreachable(0); } } } @@ -122,11 +122,11 @@ void CCState::AnalyzeCallOperands(SmallVectorImpl<MVT> &ArgVTs, MVT ArgVT = ArgVTs[i]; ISD::ArgFlagsTy ArgFlags = Flags[i]; if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) { - std::string msg; - raw_string_ostream Msg(msg); - Msg << "Call operand #" << i << " has unhandled type " +#ifndef NDEBUG + cerr << "Call operand #" << i << " has unhandled type " << ArgVT.getMVTString(); - llvm_report_error(Msg.str()); +#endif + llvm_unreachable(0); } } } @@ -140,11 +140,11 @@ void CCState::AnalyzeCallResult(CallSDNode *TheCall, CCAssignFn Fn) { if (TheCall->isInreg()) Flags.setInReg(); if (Fn(i, VT, VT, CCValAssign::Full, Flags, *this)) { - std::string msg; - raw_string_ostream Msg(msg); - Msg << "Call result #" << i << " has unhandled type " +#ifndef NDEBUG + cerr << "Call result #" << i << " has unhandled type " << VT.getMVTString(); - llvm_report_error(Msg.str()); +#endif + llvm_unreachable(0); } } } @@ -153,10 +153,10 @@ void CCState::AnalyzeCallResult(CallSDNode *TheCall, CCAssignFn Fn) { /// produce a single value. void CCState::AnalyzeCallResult(MVT VT, CCAssignFn Fn) { if (Fn(0, VT, VT, CCValAssign::Full, ISD::ArgFlagsTy(), *this)) { - std::string msg; - raw_string_ostream Msg(msg); - Msg << "Call result has unhandled type " +#ifndef NDEBUG + cerr << "Call result has unhandled type " << VT.getMVTString(); - llvm_report_error(Msg.str()); +#endif + llvm_unreachable(0); } } diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 7f233b2..632c9fd 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -393,7 +393,7 @@ static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); switch (Op.getOpcode()) { - default: LLVM_UNREACHABLE("Unknown code"); + default: llvm_unreachable("Unknown code"); case ISD::ConstantFP: { APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); V.changeSign(); @@ -2259,7 +2259,7 @@ SDValue DAGCombiner::visitXOR(SDNode *N) { if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { switch (N0.getOpcode()) { default: - LLVM_UNREACHABLE("Unhandled SetCC Equivalent!"); + llvm_unreachable("Unhandled SetCC Equivalent!"); case ISD::SETCC: return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); case ISD::SELECT_CC: @@ -5063,7 +5063,7 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) { if (Value.getOpcode() != ISD::TargetConstantFP) { SDValue Tmp; switch (CFP->getValueType(0).getSimpleVT()) { - default: LLVM_UNREACHABLE("Unknown FP type"); + default: llvm_unreachable("Unknown FP type"); case MVT::f80: // We don't do this for these yet. case MVT::f128: case MVT::ppcf128: @@ -6107,7 +6107,7 @@ bool DAGCombiner::FindAliasInfo(SDNode *N, SrcValue = ST->getSrcValue(); SrcValueOffset = ST->getSrcValueOffset(); } else { - LLVM_UNREACHABLE("FindAliasInfo expected a memory operand"); + llvm_unreachable("FindAliasInfo expected a memory operand"); } return false; diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index a40a0c3..01f3cc7 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -949,7 +949,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { #ifndef NDEBUG cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; #endif - LLVM_UNREACHABLE("Do not know how to legalize this operator!"); + llvm_unreachable("Do not know how to legalize this operator!"); case ISD::CALL: // The only option for this is to custom lower it. Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG); @@ -983,7 +983,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { return Tmp2; case ISD::BUILD_VECTOR: switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { - default: LLVM_UNREACHABLE("This action is not supported yet!"); + default: llvm_unreachable("This action is not supported yet!"); case TargetLowering::Custom: Tmp3 = TLI.LowerOperation(Result, DAG); if (Tmp3.getNode()) { @@ -1100,7 +1100,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { Tmp4 = Result.getValue(1); switch (TLI.getOperationAction(Node->getOpcode(), VT)) { - default: LLVM_UNREACHABLE("This action is not supported yet!"); + default: llvm_unreachable("This action is not supported yet!"); case TargetLowering::Legal: // If this is an unaligned load and the target doesn't support it, // expand it. @@ -1270,7 +1270,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { Tmp2 = LegalizeOp(Ch); } else { switch (TLI.getLoadExtAction(ExtType, SrcVT)) { - default: LLVM_UNREACHABLE("This action is not supported yet!"); + default: llvm_unreachable("This action is not supported yet!"); case TargetLowering::Custom: isCustom = true; // FALLTHROUGH @@ -1363,7 +1363,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { MVT VT = Tmp3.getValueType(); switch (TLI.getOperationAction(ISD::STORE, VT)) { - default: LLVM_UNREACHABLE("This action is not supported yet!"); + default: llvm_unreachable("This action is not supported yet!"); case TargetLowering::Legal: // If this is an unaligned store and the target doesn't support it, // expand it. @@ -1463,7 +1463,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { ST->getOffset()); switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { - default: LLVM_UNREACHABLE("This action is not supported yet!"); + default: llvm_unreachable("This action is not supported yet!"); case TargetLowering::Legal: // If this is an unaligned store and the target doesn't support it, // expand it. @@ -1691,7 +1691,7 @@ void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT, MVT OpVT = LHS.getValueType(); ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); switch (TLI.getCondCodeAction(CCCode, OpVT)) { - default: LLVM_UNREACHABLE("Unknown condition code action!"); + default: llvm_unreachable("Unknown condition code action!"); case TargetLowering::Legal: // Nothing to do. break; @@ -1699,7 +1699,7 @@ void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT, ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID; unsigned Opc = 0; switch (CCCode) { - default: LLVM_UNREACHABLE("Don't know how to expand this condition!"); + default: llvm_unreachable("Don't know how to expand this condition!"); case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break; case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break; case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break; @@ -1926,7 +1926,7 @@ SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node, RTLIB::Libcall Call_PPCF128) { RTLIB::Libcall LC; switch (Node->getValueType(0).getSimpleVT()) { - default: LLVM_UNREACHABLE("Unexpected request for libcall!"); + default: llvm_unreachable("Unexpected request for libcall!"); case MVT::f32: LC = Call_F32; break; case MVT::f64: LC = Call_F64; break; case MVT::f80: LC = Call_F80; break; @@ -1942,7 +1942,7 @@ SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned, RTLIB::Libcall Call_I128) { RTLIB::Libcall LC; switch (Node->getValueType(0).getSimpleVT()) { - default: LLVM_UNREACHABLE("Unexpected request for libcall!"); + default: llvm_unreachable("Unexpected request for libcall!"); case MVT::i16: LC = Call_I16; break; case MVT::i32: LC = Call_I32; break; case MVT::i64: LC = Call_I64; break; @@ -2028,7 +2028,7 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, // offset depending on the data type. uint64_t FF; switch (Op0.getValueType().getSimpleVT()) { - default: LLVM_UNREACHABLE("Unsupported integer type!"); + default: llvm_unreachable("Unsupported integer type!"); case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) @@ -2147,7 +2147,7 @@ SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) { MVT SHVT = TLI.getShiftAmountTy(); SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; switch (VT.getSimpleVT()) { - default: LLVM_UNREACHABLE("Unhandled Expand type in BSWAP!"); + default: llvm_unreachable("Unhandled Expand type in BSWAP!"); case MVT::i16: Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); @@ -2192,7 +2192,7 @@ SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) { SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl) { switch (Opc) { - default: LLVM_UNREACHABLE("Cannot expand this yet!"); + default: llvm_unreachable("Cannot expand this yet!"); case ISD::CTPOP: { static const uint64_t mask[6] = { 0x5555555555555555ULL, 0x3333333333333333ULL, @@ -2306,7 +2306,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node, else if (VT.isFloatingPoint()) Results.push_back(DAG.getConstantFP(0, VT)); else - LLVM_UNREACHABLE("Unknown value type!"); + llvm_unreachable("Unknown value type!"); break; } case ISD::TRAP: { @@ -2810,7 +2810,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node, // type in some cases cases. // Also, we can fall back to a division in some cases, but that's a big // performance hit in the general case. - LLVM_UNREACHABLE("Don't know how to expand this operation yet!"); + llvm_unreachable("Don't know how to expand this operation yet!"); } if (isSigned) { Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, TLI.getShiftAmountTy()); @@ -3102,7 +3102,7 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node, break; } if (NewInTy.isInteger()) - LLVM_UNREACHABLE("Cannot promote Legal Integer SETCC yet"); + llvm_unreachable("Cannot promote Legal Integer SETCC yet"); else { Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp1); Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp2); diff --git a/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp index 9428525..1bf5b0b 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp @@ -53,7 +53,7 @@ void DAGTypeLegalizer::SoftenFloatResult(SDNode *N, unsigned ResNo) { cerr << "SoftenFloatResult #" << ResNo << ": "; N->dump(&DAG); cerr << "\n"; #endif - LLVM_UNREACHABLE("Do not know how to soften the result of this operator!"); + llvm_unreachable("Do not know how to soften the result of this operator!"); case ISD::BIT_CONVERT: R = SoftenFloatRes_BIT_CONVERT(N); break; case ISD::BUILD_PAIR: R = SoftenFloatRes_BUILD_PAIR(N); break; @@ -541,7 +541,7 @@ bool DAGTypeLegalizer::SoftenFloatOperand(SDNode *N, unsigned OpNo) { cerr << "SoftenFloatOperand Op #" << OpNo << ": "; N->dump(&DAG); cerr << "\n"; #endif - LLVM_UNREACHABLE("Do not know how to soften this operator's operand!"); + llvm_unreachable("Do not know how to soften this operator's operand!"); case ISD::BIT_CONVERT: Res = SoftenFloatOp_BIT_CONVERT(N); break; case ISD::BR_CC: Res = SoftenFloatOp_BR_CC(N); break; @@ -781,7 +781,7 @@ void DAGTypeLegalizer::ExpandFloatResult(SDNode *N, unsigned ResNo) { cerr << "ExpandFloatResult #" << ResNo << ": "; N->dump(&DAG); cerr << "\n"; #endif - LLVM_UNREACHABLE("Do not know how to expand the result of this operator!"); + llvm_unreachable("Do not know how to expand the result of this operator!"); case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break; case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; @@ -1180,7 +1180,7 @@ bool DAGTypeLegalizer::ExpandFloatOperand(SDNode *N, unsigned OpNo) { cerr << "ExpandFloatOperand Op #" << OpNo << ": "; N->dump(&DAG); cerr << "\n"; #endif - LLVM_UNREACHABLE("Do not know how to expand this operator's operand!"); + llvm_unreachable("Do not know how to expand this operator's operand!"); case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break; case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break; diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp index 63ddbed..600185b 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -45,7 +45,7 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) { cerr << "PromoteIntegerResult #" << ResNo << ": "; N->dump(&DAG); cerr << "\n"; #endif - LLVM_UNREACHABLE("Do not know how to promote this operator!"); + llvm_unreachable("Do not know how to promote this operator!"); case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break; case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break; case ISD::BIT_CONVERT: Res = PromoteIntRes_BIT_CONVERT(N); break; @@ -491,7 +491,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) { SDValue Res; switch (getTypeAction(N->getOperand(0).getValueType())) { - default: LLVM_UNREACHABLE("Unknown type action!"); + default: llvm_unreachable("Unknown type action!"); case Legal: case ExpandInteger: Res = N->getOperand(0); @@ -610,7 +610,7 @@ bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) { cerr << "PromoteIntegerOperand Op #" << OpNo << ": "; N->dump(&DAG); cerr << "\n"; #endif - LLVM_UNREACHABLE("Do not know how to promote this operator's operand!"); + llvm_unreachable("Do not know how to promote this operator's operand!"); case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break; case ISD::BIT_CONVERT: Res = PromoteIntOp_BIT_CONVERT(N); break; @@ -666,7 +666,7 @@ void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS, // insert sign extends for ALL conditions, but zero extend is cheaper on // many machines (an AND instead of two shifts), so prefer it. switch (CCCode) { - default: LLVM_UNREACHABLE("Unknown integer comparison!"); + default: llvm_unreachable("Unknown integer comparison!"); case ISD::SETEQ: case ISD::SETNE: case ISD::SETUGE: @@ -923,7 +923,7 @@ void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) { cerr << "ExpandIntegerResult #" << ResNo << ": "; N->dump(&DAG); cerr << "\n"; #endif - LLVM_UNREACHABLE("Do not know how to expand the result of this operator!"); + llvm_unreachable("Do not know how to expand the result of this operator!"); case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break; case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; @@ -1104,7 +1104,7 @@ ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { DAG.getConstant(~HighBitMask, ShTy)); switch (N->getOpcode()) { - default: LLVM_UNREACHABLE("Unknown shift"); + default: llvm_unreachable("Unknown shift"); case ISD::SHL: Lo = DAG.getConstant(0, NVT); // Low part is zero. Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part. @@ -1132,7 +1132,7 @@ ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { Amt); unsigned Op1, Op2; switch (N->getOpcode()) { - default: LLVM_UNREACHABLE("Unknown shift"); + default: llvm_unreachable("Unknown shift"); case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break; case ISD::SRL: case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break; @@ -1172,7 +1172,7 @@ ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { SDValue Lo1, Hi1, Lo2, Hi2; switch (N->getOpcode()) { - default: LLVM_UNREACHABLE("Unknown shift"); + default: llvm_unreachable("Unknown shift"); case ISD::SHL: // ShAmt < NVTBits Lo1 = DAG.getConstant(0, NVT); // Low part is zero. @@ -1792,7 +1792,7 @@ void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N, } if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi)) - LLVM_UNREACHABLE("Unsupported shift!"); + llvm_unreachable("Unsupported shift!"); } void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N, @@ -1968,7 +1968,7 @@ bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) { cerr << "ExpandIntegerOperand Op #" << OpNo << ": "; N->dump(&DAG); cerr << "\n"; #endif - LLVM_UNREACHABLE("Do not know how to expand this operator's operand!"); + llvm_unreachable("Do not know how to expand this operator's operand!"); case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break; case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break; @@ -2050,7 +2050,7 @@ void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS, // FIXME: This generated code sucks. ISD::CondCode LowCC; switch (CCCode) { - default: LLVM_UNREACHABLE("Unknown integer setcc!"); + default: llvm_unreachable("Unknown integer setcc!"); case ISD::SETLT: case ISD::SETULT: LowCC = ISD::SETULT; break; case ISD::SETGT: diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp index f8d198a..1f05e8d 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp @@ -150,7 +150,7 @@ void DAGTypeLegalizer::PerformExpensiveChecks() { if (Mapped & 128) cerr << " WidenedVectors"; cerr << "\n"; - llvm_unreachable(); + llvm_unreachable(0); } } } @@ -432,7 +432,7 @@ NodeDone: if (Failed) { I->dump(&DAG); cerr << "\n"; - llvm_unreachable(); + llvm_unreachable(0); } } #endif diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index 013b18b..fe26609 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -41,7 +41,7 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) { cerr << "ScalarizeVectorResult #" << ResNo << ": "; N->dump(&DAG); cerr << "\n"; #endif - LLVM_UNREACHABLE("Do not know how to scalarize the result of this operator!"); + llvm_unreachable("Do not know how to scalarize the result of this operator!"); case ISD::BIT_CONVERT: R = ScalarizeVecRes_BIT_CONVERT(N); break; case ISD::BUILD_VECTOR: R = N->getOperand(0); break; @@ -278,7 +278,7 @@ bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) { cerr << "ScalarizeVectorOperand Op #" << OpNo << ": "; N->dump(&DAG); cerr << "\n"; #endif - LLVM_UNREACHABLE("Do not know how to scalarize this operator's operand!"); + llvm_unreachable("Do not know how to scalarize this operator's operand!"); case ISD::BIT_CONVERT: Res = ScalarizeVecOp_BIT_CONVERT(N); break; @@ -378,7 +378,7 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) { cerr << "SplitVectorResult #" << ResNo << ": "; N->dump(&DAG); cerr << "\n"; #endif - LLVM_UNREACHABLE("Do not know how to split the result of this operator!"); + llvm_unreachable("Do not know how to split the result of this operator!"); case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break; case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; @@ -576,7 +576,7 @@ void DAGTypeLegalizer::SplitVecRes_CONVERT_RNDSAT(SDNode *N, SDValue &Lo, SDValue VLo, VHi; MVT InVT = N->getOperand(0).getValueType(); switch (getTypeAction(InVT)) { - default: LLVM_UNREACHABLE("Unexpected type action!"); + default: llvm_unreachable("Unexpected type action!"); case Legal: { MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(), LoVT.getVectorNumElements()); @@ -768,7 +768,7 @@ void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo, // Split the input. MVT InVT = N->getOperand(0).getValueType(); switch (getTypeAction(InVT)) { - default: LLVM_UNREACHABLE("Unexpected type action!"); + default: llvm_unreachable("Unexpected type action!"); case Legal: { MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(), LoVT.getVectorNumElements()); @@ -928,7 +928,7 @@ bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) { cerr << "SplitVectorOperand Op #" << OpNo << ": "; N->dump(&DAG); cerr << "\n"; #endif - LLVM_UNREACHABLE("Do not know how to split this operator's operand!"); + llvm_unreachable("Do not know how to split this operator's operand!"); case ISD::BIT_CONVERT: Res = SplitVecOp_BIT_CONVERT(N); break; case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break; @@ -1117,7 +1117,7 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) { cerr << "WidenVectorResult #" << ResNo << ": "; N->dump(&DAG); cerr << "\n"; #endif - LLVM_UNREACHABLE("Do not know how to widen the result of this operator!"); + llvm_unreachable("Do not know how to widen the result of this operator!"); case ISD::BIT_CONVERT: Res = WidenVecRes_BIT_CONVERT(N); break; case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break; @@ -1773,7 +1773,7 @@ bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned ResNo) { cerr << "WidenVectorOperand op #" << ResNo << ": "; N->dump(&DAG); cerr << "\n"; #endif - LLVM_UNREACHABLE("Do not know how to widen this operator's operand!"); + llvm_unreachable("Do not know how to widen this operator's operand!"); case ISD::BIT_CONVERT: Res = WidenVecOp_BIT_CONVERT(N); break; case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break; diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp index 52626db..515ec91 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp @@ -140,7 +140,7 @@ void ScheduleDAGFast::ReleasePred(SUnit *SU, SDep *PredEdge) { cerr << "*** Scheduling failed! ***\n"; PredSU->dump(this); cerr << " has been released too many times!\n"; - llvm_unreachable(); + llvm_unreachable(0); } #endif @@ -569,7 +569,7 @@ void ScheduleDAGFast::ListScheduleBottomUp() { } if (!CurSU) { - LLVM_UNREACHABLE("Unable to resolve live physical register dependencies!"); + llvm_unreachable("Unable to resolve live physical register dependencies!"); } } diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp index afce348..c91ab66 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp @@ -114,7 +114,7 @@ void ScheduleDAGList::ReleaseSucc(SUnit *SU, const SDep &D) { cerr << "*** Scheduling failed! ***\n"; SuccSU->dump(this); cerr << " has been released too many times!\n"; - llvm_unreachable(); + llvm_unreachable(0); } #endif diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index 85794b9..7c30990 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -203,7 +203,7 @@ void ScheduleDAGRRList::ReleasePred(SUnit *SU, const SDep *PredEdge) { cerr << "*** Scheduling failed! ***\n"; PredSU->dump(this); cerr << " has been released too many times!\n"; - llvm_unreachable(); + llvm_unreachable(0); } #endif @@ -830,7 +830,7 @@ void ScheduleDAGRRList::ReleaseSucc(SUnit *SU, const SDep *SuccEdge) { cerr << "*** Scheduling failed! ***\n"; SuccSU->dump(this); cerr << " has been released too many times!\n"; - llvm_unreachable(); + llvm_unreachable(0); } #endif diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp index 80a8ae9..0cc8bba 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp @@ -431,7 +431,7 @@ void ScheduleDAGSDNodes::EmitSubregNode(SDNode *Node, MI->addOperand(MachineOperand::CreateImm(SubIdx)); BB->insert(InsertPos, MI); } else - LLVM_UNREACHABLE("Node is not insert_subreg, extract_subreg, or subreg_to_reg"); + llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg"); SDValue Op(Node, 0); bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; @@ -552,10 +552,10 @@ void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone, bool IsCloned, #ifndef NDEBUG Node->dump(DAG); #endif - LLVM_UNREACHABLE("This target-independent node should have been selected!"); + llvm_unreachable("This target-independent node should have been selected!"); break; case ISD::EntryToken: - LLVM_UNREACHABLE("EntryToken should have been excluded from the schedule!"); + llvm_unreachable("EntryToken should have been excluded from the schedule!"); break; case ISD::TokenFactor: // fall thru break; @@ -619,7 +619,7 @@ void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone, bool IsCloned, ++i; // Skip the ID value. switch (Flags & 7) { - default: LLVM_UNREACHABLE("Bad flags!"); + default: llvm_unreachable("Bad flags!"); case 2: // Def of register. for (; NumVals; --NumVals, ++i) { unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 98841f8..caa3ce1 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -54,7 +54,7 @@ static SDVTList makeVTList(const MVT *VTs, unsigned NumVTs) { static const fltSemantics *MVTToAPFloatSemantics(MVT VT) { switch (VT.getSimpleVT()) { - default: LLVM_UNREACHABLE("Unknown FP format"); + default: llvm_unreachable("Unknown FP format"); case MVT::f32: return &APFloat::IEEEsingle; case MVT::f64: return &APFloat::IEEEdouble; case MVT::f80: return &APFloat::x87DoubleExtended; @@ -244,7 +244,7 @@ ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) { /// if the operation does not depend on the sign of the input (setne and seteq). static int isSignedOp(ISD::CondCode Opcode) { switch (Opcode) { - default: LLVM_UNREACHABLE("Illegal integer setcc operation!"); + default: llvm_unreachable("Illegal integer setcc operation!"); case ISD::SETEQ: case ISD::SETNE: return 0; case ISD::SETLT: @@ -364,7 +364,7 @@ static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N) { switch (N->getOpcode()) { case ISD::TargetExternalSymbol: case ISD::ExternalSymbol: - LLVM_UNREACHABLE("Should only be used on nodes with operands"); + llvm_unreachable("Should only be used on nodes with operands"); default: break; // Normal nodes don't need extra info. case ISD::ARG_FLAGS: ID.AddInteger(cast<ARG_FLAGSSDNode>(N)->getArgFlags().getRawBits()); @@ -627,7 +627,7 @@ bool SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) { bool Erased = false; switch (N->getOpcode()) { case ISD::EntryToken: - LLVM_UNREACHABLE("EntryToken should not be in CSEMaps!"); + llvm_unreachable("EntryToken should not be in CSEMaps!"); return false; case ISD::HANDLENODE: return false; // noop. case ISD::CONDCODE: @@ -669,7 +669,7 @@ bool SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) { !N->isMachineOpcode() && !doNotCSE(N)) { N->dump(this); cerr << "\n"; - LLVM_UNREACHABLE("Node is not in map!"); + llvm_unreachable("Node is not in map!"); } #endif return Erased; @@ -1443,7 +1443,7 @@ SDValue SelectionDAG::FoldSetCC(MVT VT, SDValue N1, const APInt &C1 = N1C->getAPIntValue(); switch (Cond) { - default: LLVM_UNREACHABLE("Unknown integer setcc!"); + default: llvm_unreachable("Unknown integer setcc!"); case ISD::SETEQ: return getConstant(C1 == C2, VT); case ISD::SETNE: return getConstant(C1 != C2, VT); case ISD::SETULT: return getConstant(C1.ult(C2), VT); @@ -2372,7 +2372,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, case ISD::MERGE_VALUES: case ISD::CONCAT_VECTORS: return Operand; // Factor, merge or concat of one node? No need. - case ISD::FP_ROUND: LLVM_UNREACHABLE("Invalid method to make FP_ROUND node"); + case ISD::FP_ROUND: llvm_unreachable("Invalid method to make FP_ROUND node"); case ISD::FP_EXTEND: assert(VT.isFloatingPoint() && Operand.getValueType().isFloatingPoint() && "Invalid FP cast!"); @@ -2947,7 +2947,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, } break; case ISD::VECTOR_SHUFFLE: - LLVM_UNREACHABLE("should use getVectorShuffle constructor!"); + llvm_unreachable("should use getVectorShuffle constructor!"); break; case ISD::BIT_CONVERT: // Fold bit_convert nodes from a type to themselves. @@ -4061,7 +4061,7 @@ SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3, MVT VT4) { SDVTList SelectionDAG::getVTList(const MVT *VTs, unsigned NumVTs) { switch (NumVTs) { - case 0: LLVM_UNREACHABLE("Cannot have nodes without results!"); + case 0: llvm_unreachable("Cannot have nodes without results!"); case 1: return getVTList(VTs[0]); case 2: return getVTList(VTs[0], VTs[1]); case 3: return getVTList(VTs[0], VTs[1], VTs[2]); @@ -5342,7 +5342,7 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const { case ISD::CONVERT_RNDSAT: { switch (cast<CvtRndSatSDNode>(this)->getCvtCode()) { - default: LLVM_UNREACHABLE("Unknown cvt code!"); + default: llvm_unreachable("Unknown cvt code!"); case ISD::CVT_FF: return "cvt_ff"; case ISD::CVT_FS: return "cvt_fs"; case ISD::CVT_FU: return "cvt_fu"; @@ -5394,7 +5394,7 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const { case ISD::CONDCODE: switch (cast<CondCodeSDNode>(this)->get()) { - default: LLVM_UNREACHABLE("Unknown setcc condition!"); + default: llvm_unreachable("Unknown setcc condition!"); case ISD::SETOEQ: return "setoeq"; case ISD::SETOGT: return "setogt"; case ISD::SETOGE: return "setoge"; diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp index ef71a62..499939b 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp @@ -556,7 +556,7 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl, if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val); - LLVM_UNREACHABLE("Unknown mismatch!"); + llvm_unreachable("Unknown mismatch!"); return SDValue(); } @@ -592,7 +592,7 @@ static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val, ValueVT = MVT::getIntegerVT(NumParts * PartBits); Val = DAG.getNode(ExtendKind, dl, ValueVT, Val); } else { - LLVM_UNREACHABLE("Unknown mismatch!"); + llvm_unreachable("Unknown mismatch!"); } } else if (PartBits == ValueVT.getSizeInBits()) { // Different types of the same size. @@ -604,7 +604,7 @@ static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val, ValueVT = MVT::getIntegerVT(NumParts * PartBits); Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val); } else { - LLVM_UNREACHABLE("Unknown mismatch!"); + llvm_unreachable("Unknown mismatch!"); } } @@ -818,7 +818,7 @@ void SelectionDAGLowering::visit(unsigned Opcode, User &I) { // Note: this doesn't use InstVisitor, because it has to work with // ConstantExpr's in addition to instructions. switch (Opcode) { - default: LLVM_UNREACHABLE("Unknown instruction type encountered!"); + default: llvm_unreachable("Unknown instruction type encountered!"); // Build the switch statement using the Instruction.def file. #define HANDLE_INST(NUM, OPCODE, CLASS) \ case Instruction::OPCODE:return visit##OPCODE((CLASS&)I); @@ -1073,7 +1073,7 @@ static ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred) { case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; default: - LLVM_UNREACHABLE("Invalid FCmp predicate opcode!"); + llvm_unreachable("Invalid FCmp predicate opcode!"); FOC = FPC = ISD::SETFALSE; break; } @@ -1099,7 +1099,7 @@ static ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred) { case ICmpInst::ICMP_SGT: return ISD::SETGT; case ICmpInst::ICMP_UGT: return ISD::SETUGT; default: - LLVM_UNREACHABLE("Invalid ICmp predicate opcode!"); + llvm_unreachable("Invalid ICmp predicate opcode!"); return ISD::SETNE; } } @@ -1131,7 +1131,7 @@ SelectionDAGLowering::EmitBranchForMergedCondition(Value *Cond, Condition = getFCmpCondCode(FC->getPredicate()); } else { Condition = ISD::SETEQ; // silence warning. - LLVM_UNREACHABLE("Unknown compare instruction"); + llvm_unreachable("Unknown compare instruction"); } CaseBlock CB(Condition, BOp->getOperand(0), @@ -4256,7 +4256,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { case Intrinsic::gcread: case Intrinsic::gcwrite: - LLVM_UNREACHABLE("GC failed to lower gcread/gcwrite intrinsics!"); + llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!"); return 0; case Intrinsic::flt_rounds: { @@ -5763,7 +5763,7 @@ void TargetLowering::LowerOperationWrapper(SDNode *N, } SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { - LLVM_UNREACHABLE("LowerOperation not implemented for this target!"); + llvm_unreachable("LowerOperation not implemented for this target!"); return SDValue(); } diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h index deb8855..bebe5ca 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h +++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h @@ -540,10 +540,10 @@ private: void visitVACopy(CallInst &I); void visitUserOp1(Instruction &I) { - LLVM_UNREACHABLE("UserOp1 should not exist at instruction selection time!"); + llvm_unreachable("UserOp1 should not exist at instruction selection time!"); } void visitUserOp2(Instruction &I) { - LLVM_UNREACHABLE("UserOp2 should not exist at instruction selection time!"); + llvm_unreachable("UserOp2 should not exist at instruction selection time!"); } const char *implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op); diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 6d7c9c0..1f9e266 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -157,7 +157,7 @@ MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, "'usesCustomDAGSchedInserter', it must implement " "TargetLowering::EmitInstrWithCustomInserter!"; #endif - llvm_unreachable(); + llvm_unreachable(0); return 0; } @@ -878,7 +878,7 @@ void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, if (EnableFastISelAbort) // The "fast" selector couldn't handle something and bailed. // For the purpose of debugging, just abort. - LLVM_UNREACHABLE("FastISel didn't select the entire block"); + llvm_unreachable("FastISel didn't select the entire block"); } break; } diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index cddb516..dc25041 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -1841,7 +1841,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1, if (CFP->getValueAPF().isNaN()) { // If an operand is known to be a nan, we can fold it. switch (ISD::getUnorderedFlavor(Cond)) { - default: LLVM_UNREACHABLE("Unknown flavor!"); + default: llvm_unreachable("Unknown flavor!"); case 0: // Known false. return DAG.getConstant(0, VT); case 1: // Known true. @@ -2001,7 +2001,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1, SDValue Temp; if (N0.getValueType() == MVT::i1 && foldBooleans) { switch (Cond) { - default: LLVM_UNREACHABLE("Unknown integer setcc!"); + default: llvm_unreachable("Unknown integer setcc!"); case ISD::SETEQ: // X == Y -> ~(X^Y) Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); N0 = DAG.getNOT(dl, Temp, MVT::i1); @@ -2311,7 +2311,7 @@ unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const { /// is. static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { switch (CT) { - default: LLVM_UNREACHABLE("Unknown constraint type!"); + default: llvm_unreachable("Unknown constraint type!"); case TargetLowering::C_Other: case TargetLowering::C_Unknown: return 0; diff --git a/lib/CodeGen/SimpleRegisterCoalescing.cpp b/lib/CodeGen/SimpleRegisterCoalescing.cpp index cb5d3f0..ac44c86 100644 --- a/lib/CodeGen/SimpleRegisterCoalescing.cpp +++ b/lib/CodeGen/SimpleRegisterCoalescing.cpp @@ -1345,7 +1345,7 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) { DstSubIdx = CopyMI->getOperand(3).getImm(); SrcReg = CopyMI->getOperand(2).getReg(); } else if (!tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)){ - LLVM_UNREACHABLE("Unrecognized copy instruction!"); + llvm_unreachable("Unrecognized copy instruction!"); } // If they are already joined we continue. @@ -2062,7 +2062,7 @@ bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){ *tri_->getSuperRegisters(LHS.reg)) // Imprecise sub-register information. Can't handle it. return false; - LLVM_UNREACHABLE("No copies from the RHS?"); + llvm_unreachable("No copies from the RHS?"); } else { LHSValNo = EliminatedLHSVals[0]; } diff --git a/lib/CodeGen/VirtRegRewriter.cpp b/lib/CodeGen/VirtRegRewriter.cpp index 7a8b39a..69f640e 100644 --- a/lib/CodeGen/VirtRegRewriter.cpp +++ b/lib/CodeGen/VirtRegRewriter.cpp @@ -1000,7 +1000,7 @@ private: // Unfold current MI. SmallVector<MachineInstr*, 4> NewMIs; if (!TII->unfoldMemoryOperand(MF, &MI, VirtReg, false, false, NewMIs)) - LLVM_UNREACHABLE("Unable unfold the load / store folding instruction!"); + llvm_unreachable("Unable unfold the load / store folding instruction!"); assert(NewMIs.size() == 1); AssignPhysToVirtReg(NewMIs[0], VirtReg, PhysReg); VRM.transferRestorePts(&MI, NewMIs[0]); @@ -1016,7 +1016,7 @@ private: NextMII = next(NextMII); NewMIs.clear(); if (!TII->unfoldMemoryOperand(MF, &NextMI, VirtReg, false, false, NewMIs)) - LLVM_UNREACHABLE("Unable unfold the load / store folding instruction!"); + llvm_unreachable("Unable unfold the load / store folding instruction!"); assert(NewMIs.size() == 1); AssignPhysToVirtReg(NewMIs[0], VirtReg, PhysReg); VRM.transferRestorePts(&NextMI, NewMIs[0]); @@ -1452,7 +1452,7 @@ private: assert(RC && "Unable to determine register class!"); int SS = VRM.getEmergencySpillSlot(RC); if (UsedSS.count(SS)) - LLVM_UNREACHABLE("Need to spill more than one physical registers!"); + llvm_unreachable("Need to spill more than one physical registers!"); UsedSS.insert(SS); TII->storeRegToStackSlot(MBB, MII, PhysReg, true, SS, RC); MachineInstr *StoreMI = prior(MII); @@ -2177,7 +2177,7 @@ private: llvm::VirtRegRewriter* llvm::createVirtRegRewriter() { switch (RewriterOpt) { - default: LLVM_UNREACHABLE("Unreachable!"); + default: llvm_unreachable("Unreachable!"); case local: return new LocalRewriter(); case trivial: diff --git a/lib/ExecutionEngine/ExecutionEngine.cpp b/lib/ExecutionEngine/ExecutionEngine.cpp index 226cd4f..9f27338 100644 --- a/lib/ExecutionEngine/ExecutionEngine.cpp +++ b/lib/ExecutionEngine/ExecutionEngine.cpp @@ -421,7 +421,7 @@ void *ExecutionEngine::getPointerToGlobal(const GlobalValue *GV) { const_cast<GlobalVariable *>(dyn_cast<GlobalVariable>(GV))) EmitGlobalVariable(GVar); else - LLVM_UNREACHABLE("Global hasn't had an address allocated yet!"); + llvm_unreachable("Global hasn't had an address allocated yet!"); return state.getGlobalAddressMap(locked)[GV]; } @@ -548,7 +548,7 @@ GenericValue ExecutionEngine::getConstantValue(const Constant *C) { GenericValue GV = getConstantValue(Op0); const Type* DestTy = CE->getType(); switch (Op0->getType()->getTypeID()) { - default: LLVM_UNREACHABLE("Invalid bitcast operand"); + default: llvm_unreachable("Invalid bitcast operand"); case Type::IntegerTyID: assert(DestTy->isFloatingPoint() && "invalid bitcast"); if (DestTy == Type::FloatTy) @@ -587,10 +587,10 @@ GenericValue ExecutionEngine::getConstantValue(const Constant *C) { GenericValue RHS = getConstantValue(CE->getOperand(1)); GenericValue GV; switch (CE->getOperand(0)->getType()->getTypeID()) { - default: LLVM_UNREACHABLE("Bad add type!"); + default: llvm_unreachable("Bad add type!"); case Type::IntegerTyID: switch (CE->getOpcode()) { - default: LLVM_UNREACHABLE("Invalid integer opcode"); + default: llvm_unreachable("Invalid integer opcode"); case Instruction::Add: GV.IntVal = LHS.IntVal + RHS.IntVal; break; case Instruction::Sub: GV.IntVal = LHS.IntVal - RHS.IntVal; break; case Instruction::Mul: GV.IntVal = LHS.IntVal * RHS.IntVal; break; @@ -605,7 +605,7 @@ GenericValue ExecutionEngine::getConstantValue(const Constant *C) { break; case Type::FloatTyID: switch (CE->getOpcode()) { - default: LLVM_UNREACHABLE("Invalid float opcode"); + default: llvm_unreachable("Invalid float opcode"); case Instruction::FAdd: GV.FloatVal = LHS.FloatVal + RHS.FloatVal; break; case Instruction::FSub: @@ -620,7 +620,7 @@ GenericValue ExecutionEngine::getConstantValue(const Constant *C) { break; case Type::DoubleTyID: switch (CE->getOpcode()) { - default: LLVM_UNREACHABLE("Invalid double opcode"); + default: llvm_unreachable("Invalid double opcode"); case Instruction::FAdd: GV.DoubleVal = LHS.DoubleVal + RHS.DoubleVal; break; case Instruction::FSub: @@ -638,7 +638,7 @@ GenericValue ExecutionEngine::getConstantValue(const Constant *C) { case Type::FP128TyID: { APFloat apfLHS = APFloat(LHS.IntVal); switch (CE->getOpcode()) { - default: LLVM_UNREACHABLE("Invalid long double opcode");llvm_unreachable(); + default: llvm_unreachable("Invalid long double opcode");llvm_unreachable(0); case Instruction::FAdd: apfLHS.add(APFloat(RHS.IntVal), APFloat::rmNearestTiesToEven); GV.IntVal = apfLHS.bitcastToAPInt(); @@ -698,7 +698,7 @@ GenericValue ExecutionEngine::getConstantValue(const Constant *C) { else if (const GlobalVariable* GV = dyn_cast<GlobalVariable>(C)) Result = PTOGV(getOrEmitGlobalVariable(const_cast<GlobalVariable*>(GV))); else - LLVM_UNREACHABLE("Unknown constant pointer type!"); + llvm_unreachable("Unknown constant pointer type!"); break; default: std::string msg; @@ -881,7 +881,7 @@ void ExecutionEngine::InitializeMemory(const Constant *Init, void *Addr) { } cerr << "Bad Type: " << *Init->getType() << "\n"; - LLVM_UNREACHABLE("Unknown constant type to initialize memory with!"); + llvm_unreachable("Unknown constant type to initialize memory with!"); } /// EmitGlobals - Emit all of the global variables to memory, storing their diff --git a/lib/ExecutionEngine/ExecutionEngineBindings.cpp b/lib/ExecutionEngine/ExecutionEngineBindings.cpp index 43389e0..4ee2622 100644 --- a/lib/ExecutionEngine/ExecutionEngineBindings.cpp +++ b/lib/ExecutionEngine/ExecutionEngineBindings.cpp @@ -46,7 +46,7 @@ LLVMGenericValueRef LLVMCreateGenericValueOfFloat(LLVMTypeRef TyRef, double N) { GenVal->DoubleVal = N; break; default: - LLVM_UNREACHABLE("LLVMGenericValueToFloat supports only float and double."); + llvm_unreachable("LLVMGenericValueToFloat supports only float and double."); } return wrap(GenVal); } @@ -75,7 +75,7 @@ double LLVMGenericValueToFloat(LLVMTypeRef TyRef, LLVMGenericValueRef GenVal) { case Type::DoubleTyID: return unwrap(GenVal)->DoubleVal; default: - LLVM_UNREACHABLE("LLVMGenericValueToFloat supports only float and double."); + llvm_unreachable("LLVMGenericValueToFloat supports only float and double."); break; } return 0; // Not reached diff --git a/lib/ExecutionEngine/Interpreter/Execution.cpp b/lib/ExecutionEngine/Interpreter/Execution.cpp index 4a6cafe..b351ba2 100644 --- a/lib/ExecutionEngine/Interpreter/Execution.cpp +++ b/lib/ExecutionEngine/Interpreter/Execution.cpp @@ -58,7 +58,7 @@ static void executeFAddInst(GenericValue &Dest, GenericValue Src1, IMPLEMENT_BINARY_OPERATOR(+, Double); default: cerr << "Unhandled type for FAdd instruction: " << *Ty << "\n"; - llvm_unreachable(); + llvm_unreachable(0); } } @@ -69,7 +69,7 @@ static void executeFSubInst(GenericValue &Dest, GenericValue Src1, IMPLEMENT_BINARY_OPERATOR(-, Double); default: cerr << "Unhandled type for FSub instruction: " << *Ty << "\n"; - llvm_unreachable(); + llvm_unreachable(0); } } @@ -80,7 +80,7 @@ static void executeFMulInst(GenericValue &Dest, GenericValue Src1, IMPLEMENT_BINARY_OPERATOR(*, Double); default: cerr << "Unhandled type for FMul instruction: " << *Ty << "\n"; - llvm_unreachable(); + llvm_unreachable(0); } } @@ -91,7 +91,7 @@ static void executeFDivInst(GenericValue &Dest, GenericValue Src1, IMPLEMENT_BINARY_OPERATOR(/, Double); default: cerr << "Unhandled type for FDiv instruction: " << *Ty << "\n"; - llvm_unreachable(); + llvm_unreachable(0); } } @@ -106,7 +106,7 @@ static void executeFRemInst(GenericValue &Dest, GenericValue Src1, break; default: cerr << "Unhandled type for Rem instruction: " << *Ty << "\n"; - llvm_unreachable(); + llvm_unreachable(0); } } @@ -133,7 +133,7 @@ static GenericValue executeICMP_EQ(GenericValue Src1, GenericValue Src2, IMPLEMENT_POINTER_ICMP(==); default: cerr << "Unhandled type for ICMP_EQ predicate: " << *Ty << "\n"; - llvm_unreachable(); + llvm_unreachable(0); } return Dest; } @@ -146,7 +146,7 @@ static GenericValue executeICMP_NE(GenericValue Src1, GenericValue Src2, IMPLEMENT_POINTER_ICMP(!=); default: cerr << "Unhandled type for ICMP_NE predicate: " << *Ty << "\n"; - llvm_unreachable(); + llvm_unreachable(0); } return Dest; } @@ -159,7 +159,7 @@ static GenericValue executeICMP_ULT(GenericValue Src1, GenericValue Src2, IMPLEMENT_POINTER_ICMP(<); default: cerr << "Unhandled type for ICMP_ULT predicate: " << *Ty << "\n"; - llvm_unreachable(); + llvm_unreachable(0); } return Dest; } @@ -172,7 +172,7 @@ static GenericValue executeICMP_SLT(GenericValue Src1, GenericValue Src2, IMPLEMENT_POINTER_ICMP(<); default: cerr << "Unhandled type for ICMP_SLT predicate: " << *Ty << "\n"; - llvm_unreachable(); + llvm_unreachable(0); } return Dest; } @@ -185,7 +185,7 @@ static GenericValue executeICMP_UGT(GenericValue Src1, GenericValue Src2, IMPLEMENT_POINTER_ICMP(>); default: cerr << "Unhandled type for ICMP_UGT predicate: " << *Ty << "\n"; - llvm_unreachable(); + llvm_unreachable(0); } return Dest; } @@ -198,7 +198,7 @@ static GenericValue executeICMP_SGT(GenericValue Src1, GenericValue Src2, IMPLEMENT_POINTER_ICMP(>); default: cerr << "Unhandled type for ICMP_SGT predicate: " << *Ty << "\n"; - llvm_unreachable(); + llvm_unreachable(0); } return Dest; } @@ -211,7 +211,7 @@ static GenericValue executeICMP_ULE(GenericValue Src1, GenericValue Src2, IMPLEMENT_POINTER_ICMP(<=); default: cerr << "Unhandled type for ICMP_ULE predicate: " << *Ty << "\n"; - llvm_unreachable(); + llvm_unreachable(0); } return Dest; } @@ -224,7 +224,7 @@ static GenericValue executeICMP_SLE(GenericValue Src1, GenericValue Src2, IMPLEMENT_POINTER_ICMP(<=); default: cerr << "Unhandled type for ICMP_SLE predicate: " << *Ty << "\n"; - llvm_unreachable(); + llvm_unreachable(0); } return Dest; } @@ -237,7 +237,7 @@ static GenericValue executeICMP_UGE(GenericValue Src1, GenericValue Src2, IMPLEMENT_POINTER_ICMP(>=); default: cerr << "Unhandled type for ICMP_UGE predicate: " << *Ty << "\n"; - llvm_unreachable(); + llvm_unreachable(0); } return Dest; } @@ -250,7 +250,7 @@ static GenericValue executeICMP_SGE(GenericValue Src1, GenericValue Src2, IMPLEMENT_POINTER_ICMP(>=); default: cerr << "Unhandled type for ICMP_SGE predicate: " << *Ty << "\n"; - llvm_unreachable(); + llvm_unreachable(0); } return Dest; } @@ -275,7 +275,7 @@ void Interpreter::visitICmpInst(ICmpInst &I) { case ICmpInst::ICMP_SGE: R = executeICMP_SGE(Src1, Src2, Ty); break; default: cerr << "Don't know how to handle this ICmp predicate!\n-->" << I; - llvm_unreachable(); + llvm_unreachable(0); } SetValue(&I, R, SF); @@ -294,7 +294,7 @@ static GenericValue executeFCMP_OEQ(GenericValue Src1, GenericValue Src2, IMPLEMENT_FCMP(==, Double); default: cerr << "Unhandled type for FCmp EQ instruction: " << *Ty << "\n"; - llvm_unreachable(); + llvm_unreachable(0); } return Dest; } @@ -308,7 +308,7 @@ static GenericValue executeFCMP_ONE(GenericValue Src1, GenericValue Src2, default: cerr << "Unhandled type for FCmp NE instruction: " << *Ty << "\n"; - llvm_unreachable(); + llvm_unreachable(0); } return Dest; } @@ -321,7 +321,7 @@ static GenericValue executeFCMP_OLE(GenericValue Src1, GenericValue Src2, IMPLEMENT_FCMP(<=, Double); default: cerr << "Unhandled type for FCmp LE instruction: " << *Ty << "\n"; - llvm_unreachable(); + llvm_unreachable(0); } return Dest; } @@ -334,7 +334,7 @@ static GenericValue executeFCMP_OGE(GenericValue Src1, GenericValue Src2, IMPLEMENT_FCMP(>=, Double); default: cerr << "Unhandled type for FCmp GE instruction: " << *Ty << "\n"; - llvm_unreachable(); + llvm_unreachable(0); } return Dest; } @@ -347,7 +347,7 @@ static GenericValue executeFCMP_OLT(GenericValue Src1, GenericValue Src2, IMPLEMENT_FCMP(<, Double); default: cerr << "Unhandled type for FCmp LT instruction: " << *Ty << "\n"; - llvm_unreachable(); + llvm_unreachable(0); } return Dest; } @@ -360,7 +360,7 @@ static GenericValue executeFCMP_OGT(GenericValue Src1, GenericValue Src2, IMPLEMENT_FCMP(>, Double); default: cerr << "Unhandled type for FCmp GT instruction: " << *Ty << "\n"; - llvm_unreachable(); + llvm_unreachable(0); } return Dest; } @@ -469,7 +469,7 @@ void Interpreter::visitFCmpInst(FCmpInst &I) { case FCmpInst::FCMP_OGE: R = executeFCMP_OGE(Src1, Src2, Ty); break; default: cerr << "Don't know how to handle this FCmp predicate!\n-->" << I; - llvm_unreachable(); + llvm_unreachable(0); } SetValue(&I, R, SF); @@ -515,7 +515,7 @@ static GenericValue executeCmpInst(unsigned predicate, GenericValue Src1, } default: cerr << "Unhandled Cmp predicate\n"; - llvm_unreachable(); + llvm_unreachable(0); } } @@ -544,7 +544,7 @@ void Interpreter::visitBinaryOperator(BinaryOperator &I) { case Instruction::Xor: R.IntVal = Src1.IntVal ^ Src2.IntVal; break; default: cerr << "Don't know how to handle this binary operator!\n-->" << I; - llvm_unreachable(); + llvm_unreachable(0); } SetValue(&I, R, SF); @@ -1079,7 +1079,7 @@ GenericValue Interpreter::executeBitCastInst(Value *SrcVal, const Type *DstTy, } else if (SrcTy->isInteger()) { Dest.IntVal = Src.IntVal; } else - LLVM_UNREACHABLE("Invalid BitCast"); + llvm_unreachable("Invalid BitCast"); } else if (DstTy == Type::FloatTy) { if (SrcTy->isInteger()) Dest.FloatVal = Src.IntVal.bitsToFloat(); @@ -1091,7 +1091,7 @@ GenericValue Interpreter::executeBitCastInst(Value *SrcVal, const Type *DstTy, else Dest.DoubleVal = Src.DoubleVal; } else - LLVM_UNREACHABLE("Invalid Bitcast"); + llvm_unreachable("Invalid Bitcast"); return Dest; } @@ -1176,7 +1176,7 @@ void Interpreter::visitVAArgInst(VAArgInst &I) { IMPLEMENT_VAARG(Double); default: cerr << "Unhandled dest type for vaarg instruction: " << *Ty << "\n"; - llvm_unreachable(); + llvm_unreachable(0); } // Set the Value of this Instruction. @@ -1263,7 +1263,7 @@ GenericValue Interpreter::getConstantExprValue (ConstantExpr *CE, break; default: cerr << "Unhandled ConstantExpr: " << *CE << "\n"; - llvm_unreachable(); + llvm_unreachable(0); return GenericValue(); } return Dest; @@ -1345,7 +1345,7 @@ void Interpreter::run() { DOUT << " --> "; const GenericValue &Val = SF.Values[&I]; switch (I.getType()->getTypeID()) { - default: LLVM_UNREACHABLE("Invalid GenericValue Type"); + default: llvm_unreachable("Invalid GenericValue Type"); case Type::VoidTyID: DOUT << "void"; break; case Type::FloatTyID: DOUT << "float " << Val.FloatVal; break; case Type::DoubleTyID: DOUT << "double " << Val.DoubleVal; break; diff --git a/lib/ExecutionEngine/Interpreter/Interpreter.h b/lib/ExecutionEngine/Interpreter/Interpreter.h index f9d4770..01771cf 100644 --- a/lib/ExecutionEngine/Interpreter/Interpreter.h +++ b/lib/ExecutionEngine/Interpreter/Interpreter.h @@ -147,7 +147,7 @@ public: void visitStoreInst(StoreInst &I); void visitGetElementPtrInst(GetElementPtrInst &I); void visitPHINode(PHINode &PN) { - LLVM_UNREACHABLE("PHI nodes already handled!"); + llvm_unreachable("PHI nodes already handled!"); } void visitTruncInst(TruncInst &I); void visitZExtInst(ZExtInst &I); @@ -177,7 +177,7 @@ public: void visitVAArgInst(VAArgInst &I); void visitInstruction(Instruction &I) { cerr << I; - LLVM_UNREACHABLE("Instruction not interpretable yet!"); + llvm_unreachable("Instruction not interpretable yet!"); } GenericValue callExternalFunction(Function *F, diff --git a/lib/ExecutionEngine/JIT/JIT.cpp b/lib/ExecutionEngine/JIT/JIT.cpp index 3edea73..baa8a47 100644 --- a/lib/ExecutionEngine/JIT/JIT.cpp +++ b/lib/ExecutionEngine/JIT/JIT.cpp @@ -410,7 +410,7 @@ GenericValue JIT::runFunction(Function *F, if (ArgValues.empty()) { GenericValue rv; switch (RetTy->getTypeID()) { - default: LLVM_UNREACHABLE("Unknown return type for function call!"); + default: llvm_unreachable("Unknown return type for function call!"); case Type::IntegerTyID: { unsigned BitWidth = cast<IntegerType>(RetTy)->getBitWidth(); if (BitWidth == 1) @@ -424,7 +424,7 @@ GenericValue JIT::runFunction(Function *F, else if (BitWidth <= 64) rv.IntVal = APInt(BitWidth, ((int64_t(*)())(intptr_t)FPtr)()); else - LLVM_UNREACHABLE("Integer types > 64 bits not supported"); + llvm_unreachable("Integer types > 64 bits not supported"); return rv; } case Type::VoidTyID: @@ -439,7 +439,7 @@ GenericValue JIT::runFunction(Function *F, case Type::X86_FP80TyID: case Type::FP128TyID: case Type::PPC_FP128TyID: - LLVM_UNREACHABLE("long double not supported yet"); + llvm_unreachable("long double not supported yet"); return rv; case Type::PointerTyID: return PTOGV(((void*(*)())(intptr_t)FPtr)()); @@ -467,7 +467,7 @@ GenericValue JIT::runFunction(Function *F, const Type *ArgTy = FTy->getParamType(i); const GenericValue &AV = ArgValues[i]; switch (ArgTy->getTypeID()) { - default: LLVM_UNREACHABLE("Unknown argument type for function call!"); + default: llvm_unreachable("Unknown argument type for function call!"); case Type::IntegerTyID: C = ConstantInt::get(AV.IntVal); break; diff --git a/lib/ExecutionEngine/JIT/JITDwarfEmitter.cpp b/lib/ExecutionEngine/JIT/JITDwarfEmitter.cpp index 86218f7..c661168 100644 --- a/lib/ExecutionEngine/JIT/JITDwarfEmitter.cpp +++ b/lib/ExecutionEngine/JIT/JITDwarfEmitter.cpp @@ -111,7 +111,7 @@ JITDwarfEmitter::EmitFrameMoves(intptr_t BaseLabelPtr, JCE->emitULEB128Bytes(Offset); } else { - LLVM_UNREACHABLE("Machine move no supported yet."); + llvm_unreachable("Machine move no supported yet."); } } else if (Src.isReg() && Src.getReg() == MachineLocation::VirtualFP) { @@ -119,7 +119,7 @@ JITDwarfEmitter::EmitFrameMoves(intptr_t BaseLabelPtr, JCE->emitByte(dwarf::DW_CFA_def_cfa_register); JCE->emitULEB128Bytes(RI->getDwarfRegNum(Dst.getReg(), true)); } else { - LLVM_UNREACHABLE("Machine move no supported yet."); + llvm_unreachable("Machine move no supported yet."); } } else { unsigned Reg = RI->getDwarfRegNum(Src.getReg(), true); @@ -762,7 +762,7 @@ JITDwarfEmitter::GetFrameMovesSizeInBytes(intptr_t BaseLabelPtr, FinalSize += TargetAsmInfo::getULEB128Size(Offset); } else { - LLVM_UNREACHABLE("Machine move no supported yet."); + llvm_unreachable("Machine move no supported yet."); } } else if (Src.isReg() && Src.getReg() == MachineLocation::VirtualFP) { @@ -771,7 +771,7 @@ JITDwarfEmitter::GetFrameMovesSizeInBytes(intptr_t BaseLabelPtr, unsigned RegNum = RI->getDwarfRegNum(Dst.getReg(), true); FinalSize += TargetAsmInfo::getULEB128Size(RegNum); } else { - LLVM_UNREACHABLE("Machine move no supported yet."); + llvm_unreachable("Machine move no supported yet."); } } else { unsigned Reg = RI->getDwarfRegNum(Src.getReg(), true); diff --git a/lib/Linker/LinkItems.cpp b/lib/Linker/LinkItems.cpp index a4e7db5..db86005 100644 --- a/lib/Linker/LinkItems.cpp +++ b/lib/Linker/LinkItems.cpp @@ -81,7 +81,7 @@ bool Linker::LinkInLibrary(const std::string& Lib, bool& is_native) { std::string Magic; Pathname.getMagicNumber(Magic, 64); switch (sys::IdentifyFileType(Magic.c_str(), 64)) { - default: LLVM_UNREACHABLE("Bad file type identification"); + default: llvm_unreachable("Bad file type identification"); case sys::Unknown_FileType: return warning("Supposed library '" + Lib + "' isn't a library."); @@ -179,7 +179,7 @@ bool Linker::LinkInFile(const sys::Path &File, bool &is_native) { std::string Magic; File.getMagicNumber(Magic, 64); switch (sys::IdentifyFileType(Magic.c_str(), 64)) { - default: LLVM_UNREACHABLE("Bad file type identification"); + default: llvm_unreachable("Bad file type identification"); case sys::Unknown_FileType: return warning("Ignoring file '" + File.toString() + "' because does not contain bitcode."); diff --git a/lib/Linker/LinkModules.cpp b/lib/Linker/LinkModules.cpp index 3b1fceb..85ba933 100644 --- a/lib/Linker/LinkModules.cpp +++ b/lib/Linker/LinkModules.cpp @@ -393,7 +393,7 @@ static Value *RemapOperand(const Value *In, Result = CE->getWithOperands(Ops); } else { assert(!isa<GlobalValue>(CPV) && "Unmapped global?"); - LLVM_UNREACHABLE("Unknown type of derived type constant value!"); + llvm_unreachable("Unknown type of derived type constant value!"); } } else if (isa<InlineAsm>(In)) { Result = const_cast<Value*>(In); @@ -410,7 +410,7 @@ static Value *RemapOperand(const Value *In, PrintMap(ValueMap); cerr << "Couldn't remap value: " << (void*)In << " " << *In << "\n"; - LLVM_UNREACHABLE("Couldn't remap value!"); + llvm_unreachable("Couldn't remap value!"); #endif return 0; } @@ -900,9 +900,9 @@ static bool LinkGlobalInits(Module *Dest, const Module *Src, // Nothing is required, mapped values will take the new global // automatically. } else if (DGVar->hasAppendingLinkage()) { - LLVM_UNREACHABLE("Appending linkage unimplemented!"); + llvm_unreachable("Appending linkage unimplemented!"); } else { - LLVM_UNREACHABLE("Unknown linkage!"); + llvm_unreachable("Unknown linkage!"); } } else { // Copy the initializer over now... diff --git a/lib/MC/MCAsmStreamer.cpp b/lib/MC/MCAsmStreamer.cpp index c796255..b8e71ce 100644 --- a/lib/MC/MCAsmStreamer.cpp +++ b/lib/MC/MCAsmStreamer.cpp @@ -204,7 +204,7 @@ void MCAsmStreamer::EmitValue(const MCValue &Value, unsigned Size) { // Need target hooks to know how to print this. switch (Size) { default: - LLVM_UNREACHABLE("Invalid size for machine code value!"); + llvm_unreachable("Invalid size for machine code value!"); case 1: OS << ".byte"; break; case 2: OS << ".short"; break; case 4: OS << ".long"; break; @@ -225,9 +225,9 @@ void MCAsmStreamer::EmitValueToAlignment(unsigned ByteAlignment, int64_t Value, switch (ValueSize) { default: - LLVM_UNREACHABLE("Invalid size for machine code value!"); + llvm_unreachable("Invalid size for machine code value!"); case 8: - LLVM_UNREACHABLE("Unsupported alignment size!"); + llvm_unreachable("Unsupported alignment size!"); case 1: OS << (IsPow2 ? ".p2align" : ".balign"); break; case 2: OS << (IsPow2 ? ".p2alignw" : ".balignw"); break; case 4: OS << (IsPow2 ? ".p2alignl" : ".balignl"); break; diff --git a/lib/Support/APFloat.cpp b/lib/Support/APFloat.cpp index 29bf0b4..214abec 100644 --- a/lib/Support/APFloat.cpp +++ b/lib/Support/APFloat.cpp @@ -1069,7 +1069,7 @@ APFloat::roundAwayFromZero(roundingMode rounding_mode, switch (rounding_mode) { default: - llvm_unreachable(); + llvm_unreachable(0); case rmNearestTiesToAway: return lost_fraction == lfExactlyHalf || lost_fraction == lfMoreThanHalf; @@ -1208,7 +1208,7 @@ APFloat::addOrSubtractSpecials(const APFloat &rhs, bool subtract) { switch (convolve(category, rhs.category)) { default: - llvm_unreachable(); + llvm_unreachable(0); case convolve(fcNaN, fcZero): case convolve(fcNaN, fcNormal): @@ -1332,7 +1332,7 @@ APFloat::multiplySpecials(const APFloat &rhs) { switch (convolve(category, rhs.category)) { default: - llvm_unreachable(); + llvm_unreachable(0); case convolve(fcNaN, fcZero): case convolve(fcNaN, fcNormal): @@ -1374,7 +1374,7 @@ APFloat::divideSpecials(const APFloat &rhs) { switch (convolve(category, rhs.category)) { default: - llvm_unreachable(); + llvm_unreachable(0); case convolve(fcNaN, fcZero): case convolve(fcNaN, fcNormal): @@ -1416,7 +1416,7 @@ APFloat::modSpecials(const APFloat &rhs) { switch (convolve(category, rhs.category)) { default: - llvm_unreachable(); + llvm_unreachable(0); case convolve(fcNaN, fcZero): case convolve(fcNaN, fcNormal): @@ -1693,7 +1693,7 @@ APFloat::compare(const APFloat &rhs) const switch (convolve(category, rhs.category)) { default: - llvm_unreachable(); + llvm_unreachable(0); case convolve(fcNaN, fcZero): case convolve(fcNaN, fcNormal): @@ -2930,7 +2930,7 @@ APFloat::initFromAPInt(const APInt& api, bool isIEEE) else if (api.getBitWidth()==128 && !isIEEE) return initFromPPCDoubleDoubleAPInt(api); else - llvm_unreachable(); + llvm_unreachable(0); } APFloat::APFloat(const APInt& api, bool isIEEE) diff --git a/lib/Support/APInt.cpp b/lib/Support/APInt.cpp index 71aae6d..a034fd1 100644 --- a/lib/Support/APInt.cpp +++ b/lib/Support/APInt.cpp @@ -1387,7 +1387,7 @@ APInt APInt::sqrt() const { else return x_old + 1; } else - LLVM_UNREACHABLE("Error in APInt::sqrt computation"); + llvm_unreachable("Error in APInt::sqrt computation"); return x_old + 1; } @@ -2033,7 +2033,7 @@ void APInt::fromString(unsigned numbits, const char *str, unsigned slen, char cdigit = str[i]; if (radix == 16) { if (!isxdigit(cdigit)) - LLVM_UNREACHABLE("Invalid hex digit in string"); + llvm_unreachable("Invalid hex digit in string"); if (isdigit(cdigit)) digit = cdigit - '0'; else if (cdigit >= 'a') @@ -2041,7 +2041,7 @@ void APInt::fromString(unsigned numbits, const char *str, unsigned slen, else if (cdigit >= 'A') digit = cdigit - 'A' + 10; else - LLVM_UNREACHABLE("huh? we shouldn't get here"); + llvm_unreachable("huh? we shouldn't get here"); } else if (isdigit(cdigit)) { digit = cdigit - '0'; assert((radix == 10 || @@ -2049,7 +2049,7 @@ void APInt::fromString(unsigned numbits, const char *str, unsigned slen, (radix == 2 && (digit == 0 || digit == 1))) && "Invalid digit in string for given radix"); } else { - LLVM_UNREACHABLE("Invalid character in digit string"); + llvm_unreachable("Invalid character in digit string"); } // Shift or multiply the value by the radix diff --git a/lib/Support/CommandLine.cpp b/lib/Support/CommandLine.cpp index 400241f..34200f7 100644 --- a/lib/Support/CommandLine.cpp +++ b/lib/Support/CommandLine.cpp @@ -205,7 +205,7 @@ static inline bool ProvideOption(Option *Handler, const char *ArgName, cerr << ProgramName << ": Bad ValueMask flag! CommandLine usage error:" << Handler->getValueExpectedFlag() << "\n"; - llvm_unreachable(); + llvm_unreachable(0); } // If this isn't a multi-arg option, just run the handler. @@ -693,7 +693,7 @@ void cl::ParseCommandLineOptions(int argc, char **argv, ValNo++; break; default: - LLVM_UNREACHABLE("Internal error, unexpected NumOccurrences flag in " + llvm_unreachable("Internal error, unexpected NumOccurrences flag in " "positional argument processing!"); } } diff --git a/lib/Support/Dwarf.cpp b/lib/Support/Dwarf.cpp index c2ce680..8b688ca 100644 --- a/lib/Support/Dwarf.cpp +++ b/lib/Support/Dwarf.cpp @@ -84,7 +84,7 @@ const char *TagString(unsigned Tag) { case DW_TAG_lo_user: return "DW_TAG_lo_user"; case DW_TAG_hi_user: return "DW_TAG_hi_user"; } - LLVM_UNREACHABLE("Unknown Dwarf Tag"); + llvm_unreachable("Unknown Dwarf Tag"); return ""; } @@ -95,7 +95,7 @@ const char *ChildrenString(unsigned Children) { case DW_CHILDREN_no: return "CHILDREN_no"; case DW_CHILDREN_yes: return "CHILDREN_yes"; } - LLVM_UNREACHABLE("Unknown Dwarf ChildrenFlag"); + llvm_unreachable("Unknown Dwarf ChildrenFlag"); return ""; } @@ -206,7 +206,7 @@ const char *AttributeString(unsigned Attribute) { case DW_AT_APPLE_major_runtime_vers: return "DW_AT_APPLE_major_runtime_vers"; case DW_AT_APPLE_runtime_class: return "DW_AT_APPLE_runtime_class"; } - LLVM_UNREACHABLE("Unknown Dwarf Attribute"); + llvm_unreachable("Unknown Dwarf Attribute"); return ""; } @@ -236,7 +236,7 @@ const char *FormEncodingString(unsigned Encoding) { case DW_FORM_ref_udata: return "FORM_ref_udata"; case DW_FORM_indirect: return "FORM_indirect"; } - LLVM_UNREACHABLE("Unknown Dwarf Form Encoding"); + llvm_unreachable("Unknown Dwarf Form Encoding"); return ""; } @@ -311,7 +311,7 @@ const char *OperationEncodingString(unsigned Encoding) { case DW_OP_lo_user: return "OP_lo_user"; case DW_OP_hi_user: return "OP_hi_user"; } - LLVM_UNREACHABLE("Unknown Dwarf Operation Encoding"); + llvm_unreachable("Unknown Dwarf Operation Encoding"); return ""; } @@ -337,7 +337,7 @@ const char *AttributeEncodingString(unsigned Encoding) { case DW_ATE_lo_user: return "ATE_lo_user"; case DW_ATE_hi_user: return "ATE_hi_user"; } - LLVM_UNREACHABLE("Unknown Dwarf Attribute Encoding"); + llvm_unreachable("Unknown Dwarf Attribute Encoding"); return ""; } @@ -351,7 +351,7 @@ const char *DecimalSignString(unsigned Sign) { case DW_DS_leading_separate: return "DS_leading_separate"; case DW_DS_trailing_separate: return "DS_trailing_separate"; } - LLVM_UNREACHABLE("Unknown Dwarf Decimal Sign Attribute"); + llvm_unreachable("Unknown Dwarf Decimal Sign Attribute"); return ""; } @@ -365,7 +365,7 @@ const char *EndianityString(unsigned Endian) { case DW_END_lo_user: return "END_lo_user"; case DW_END_hi_user: return "END_hi_user"; } - LLVM_UNREACHABLE("Unknown Dwarf Endianity"); + llvm_unreachable("Unknown Dwarf Endianity"); return ""; } @@ -378,7 +378,7 @@ const char *AccessibilityString(unsigned Access) { case DW_ACCESS_protected: return "ACCESS_protected"; case DW_ACCESS_private: return "ACCESS_private"; } - LLVM_UNREACHABLE("Unknown Dwarf Accessibility"); + llvm_unreachable("Unknown Dwarf Accessibility"); return ""; } @@ -390,7 +390,7 @@ const char *VisibilityString(unsigned Visibility) { case DW_VIS_exported: return "VIS_exported"; case DW_VIS_qualified: return "VIS_qualified"; } - LLVM_UNREACHABLE("Unknown Dwarf Visibility"); + llvm_unreachable("Unknown Dwarf Visibility"); return ""; } @@ -402,7 +402,7 @@ const char *VirtualityString(unsigned Virtuality) { case DW_VIRTUALITY_virtual: return "VIRTUALITY_virtual"; case DW_VIRTUALITY_pure_virtual: return "VIRTUALITY_pure_virtual"; } - LLVM_UNREACHABLE("Unknown Dwarf Virtuality"); + llvm_unreachable("Unknown Dwarf Virtuality"); return ""; } @@ -432,7 +432,7 @@ const char *LanguageString(unsigned Language) { case DW_LANG_lo_user: return "LANG_lo_user"; case DW_LANG_hi_user: return "LANG_hi_user"; } - LLVM_UNREACHABLE("Unknown Dwarf Language"); + llvm_unreachable("Unknown Dwarf Language"); return ""; } @@ -445,7 +445,7 @@ const char *CaseString(unsigned Case) { case DW_ID_down_case: return "ID_down_case"; case DW_ID_case_insensitive: return "ID_case_insensitive"; } - LLVM_UNREACHABLE("Unknown Dwarf Identifier Case"); + llvm_unreachable("Unknown Dwarf Identifier Case"); return ""; } @@ -459,7 +459,7 @@ const char *ConventionString(unsigned Convention) { case DW_CC_lo_user: return "CC_lo_user"; case DW_CC_hi_user: return "CC_hi_user"; } - LLVM_UNREACHABLE("Unknown Dwarf Calling Convention"); + llvm_unreachable("Unknown Dwarf Calling Convention"); return ""; } @@ -472,7 +472,7 @@ const char *InlineCodeString(unsigned Code) { case DW_INL_declared_not_inlined: return "INL_declared_not_inlined"; case DW_INL_declared_inlined: return "INL_declared_inlined"; } - LLVM_UNREACHABLE("Unknown Dwarf Inline Code"); + llvm_unreachable("Unknown Dwarf Inline Code"); return ""; } @@ -483,7 +483,7 @@ const char *ArrayOrderString(unsigned Order) { case DW_ORD_row_major: return "ORD_row_major"; case DW_ORD_col_major: return "ORD_col_major"; } - LLVM_UNREACHABLE("Unknown Dwarf Array Order"); + llvm_unreachable("Unknown Dwarf Array Order"); return ""; } @@ -494,7 +494,7 @@ const char *DiscriminantString(unsigned Discriminant) { case DW_DSC_label: return "DSC_label"; case DW_DSC_range: return "DSC_range"; } - LLVM_UNREACHABLE("Unknown Dwarf Discriminant Descriptor"); + llvm_unreachable("Unknown Dwarf Discriminant Descriptor"); return ""; } @@ -515,7 +515,7 @@ const char *LNStandardString(unsigned Standard) { case DW_LNS_set_epilogue_begin: return "LNS_set_epilogue_begin"; case DW_LNS_set_isa: return "LNS_set_isa"; } - LLVM_UNREACHABLE("Unknown Dwarf Line Number Standard"); + llvm_unreachable("Unknown Dwarf Line Number Standard"); return ""; } @@ -530,7 +530,7 @@ const char *LNExtendedString(unsigned Encoding) { case DW_LNE_lo_user: return "LNE_lo_user"; case DW_LNE_hi_user: return "LNE_hi_user"; } - LLVM_UNREACHABLE("Unknown Dwarf Line Number Extended Opcode Encoding"); + llvm_unreachable("Unknown Dwarf Line Number Extended Opcode Encoding"); return ""; } @@ -545,7 +545,7 @@ const char *MacinfoString(unsigned Encoding) { case DW_MACINFO_end_file: return "MACINFO_end_file"; case DW_MACINFO_vendor_ext: return "MACINFO_vendor_ext"; } - LLVM_UNREACHABLE("Unknown Dwarf Macinfo Type Encodings"); + llvm_unreachable("Unknown Dwarf Macinfo Type Encodings"); return ""; } @@ -581,7 +581,7 @@ const char *CallFrameString(unsigned Encoding) { case DW_CFA_lo_user: return "CFA_lo_user"; case DW_CFA_hi_user: return "CFA_hi_user"; } - LLVM_UNREACHABLE("Unknown Dwarf Call Frame Instruction Encodings"); + llvm_unreachable("Unknown Dwarf Call Frame Instruction Encodings"); return ""; } diff --git a/lib/Support/ErrorHandling.cpp b/lib/Support/ErrorHandling.cpp index be0b380..e1ee188 100644 --- a/lib/Support/ErrorHandling.cpp +++ b/lib/Support/ErrorHandling.cpp @@ -44,7 +44,7 @@ void llvm_report_error(const std::string &reason) { exit(1); } -void llvm_unreachable(const char *msg, const char *file, unsigned line) { +void llvm_unreachable_internal(const char *msg, const char *file, unsigned line) { if (msg) errs() << msg << "\n"; errs() << "UNREACHABLE executed"; diff --git a/lib/Support/FoldingSet.cpp b/lib/Support/FoldingSet.cpp index 0f61067..187ecdb 100644 --- a/lib/Support/FoldingSet.cpp +++ b/lib/Support/FoldingSet.cpp @@ -51,7 +51,7 @@ void FoldingSetNodeID::AddInteger(unsigned long I) { else if (sizeof(long) == sizeof(long long)) { AddInteger((unsigned long long)I); } else { - LLVM_UNREACHABLE("unexpected sizeof(long)"); + llvm_unreachable("unexpected sizeof(long)"); } } void FoldingSetNodeID::AddInteger(long long I) { diff --git a/lib/Target/ARM/ARM.h b/lib/Target/ARM/ARM.h index 471c212..3c0cfa5 100644 --- a/lib/Target/ARM/ARM.h +++ b/lib/Target/ARM/ARM.h @@ -52,7 +52,7 @@ namespace ARMCC { inline static CondCodes getOppositeCondition(CondCodes CC){ switch (CC) { - default: LLVM_UNREACHABLE("Unknown condition code"); + default: llvm_unreachable("Unknown condition code"); case EQ: return NE; case NE: return EQ; case HS: return LO; @@ -73,7 +73,7 @@ namespace ARMCC { inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) { switch (CC) { - default: LLVM_UNREACHABLE("Unknown condition code"); + default: llvm_unreachable("Unknown condition code"); case ARMCC::EQ: return "eq"; case ARMCC::NE: return "ne"; case ARMCC::HS: return "hs"; diff --git a/lib/Target/ARM/ARMAddressingModes.h b/lib/Target/ARM/ARMAddressingModes.h index 40e3e86..5bbf35d 100644 --- a/lib/Target/ARM/ARMAddressingModes.h +++ b/lib/Target/ARM/ARMAddressingModes.h @@ -38,7 +38,7 @@ namespace ARM_AM { static inline const char *getShiftOpcStr(ShiftOpc Op) { switch (Op) { - default: LLVM_UNREACHABLE("Unknown shift opc!"); + default: llvm_unreachable("Unknown shift opc!"); case ARM_AM::asr: return "asr"; case ARM_AM::lsl: return "lsl"; case ARM_AM::lsr: return "lsr"; @@ -71,7 +71,7 @@ namespace ARM_AM { static inline const char *getAMSubModeStr(AMSubMode Mode) { switch (Mode) { - default: LLVM_UNREACHABLE("Unknown addressing sub-mode!"); + default: llvm_unreachable("Unknown addressing sub-mode!"); case ARM_AM::ia: return "ia"; case ARM_AM::ib: return "ib"; case ARM_AM::da: return "da"; @@ -81,7 +81,7 @@ namespace ARM_AM { static inline const char *getAMSubModeAltStr(AMSubMode Mode, bool isLD) { switch (Mode) { - default: LLVM_UNREACHABLE("Unknown addressing sub-mode!"); + default: llvm_unreachable("Unknown addressing sub-mode!"); case ARM_AM::ia: return isLD ? "fd" : "ea"; case ARM_AM::ib: return isLD ? "ed" : "fa"; case ARM_AM::da: return isLD ? "fa" : "ed"; diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp index 9bca6a7..a8a519a 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -434,7 +434,7 @@ unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { return 0; switch (MI->getOpcode()) { default: - LLVM_UNREACHABLE("Unknown or unset size field for instr!"); + llvm_unreachable("Unknown or unset size field for instr!"); case TargetInstrInfo::IMPLICIT_DEF: case TargetInstrInfo::DECLARE: case TargetInstrInfo::DBG_LABEL: diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/lib/Target/ARM/ARMBaseRegisterInfo.cpp index 41b061a..53ce753 100644 --- a/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -72,7 +72,7 @@ unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum) { case S30: return 30; case S31: return 31; default: - LLVM_UNREACHABLE("Unknown ARM register!"); + llvm_unreachable("Unknown ARM register!"); } } @@ -83,7 +83,7 @@ unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum, using namespace ARM; switch (RegEnum) { default: - LLVM_UNREACHABLE("Unknown ARM register!"); + llvm_unreachable("Unknown ARM register!"); case R0: case D0: return 0; case R1: case D1: return 1; case R2: case D2: return 2; @@ -707,12 +707,12 @@ unsigned ARMBaseRegisterInfo::getFrameRegister(MachineFunction &MF) const { } unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const { - LLVM_UNREACHABLE("What is the exception register"); + llvm_unreachable("What is the exception register"); return 0; } unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const { - LLVM_UNREACHABLE("What is the exception handler register"); + llvm_unreachable("What is the exception handler register"); return 0; } @@ -1138,7 +1138,7 @@ eliminateFrameIndex(MachineBasicBlock::iterator II, break; } default: - LLVM_UNREACHABLE("Unsupported addressing mode!"); + llvm_unreachable("Unsupported addressing mode!"); break; } diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp index 696547d..3442fcd 100644 --- a/lib/Target/ARM/ARMCodeEmitter.cpp +++ b/lib/Target/ARM/ARMCodeEmitter.cpp @@ -223,7 +223,7 @@ bool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) { template<class CodeEmitter> unsigned Emitter<CodeEmitter>::getShiftOp(unsigned Imm) const { switch (ARM_AM::getAM2ShiftOpc(Imm)) { - default: LLVM_UNREACHABLE("Unknown shift opc!"); + default: llvm_unreachable("Unknown shift opc!"); case ARM_AM::asr: return 2; case ARM_AM::lsl: return 0; case ARM_AM::lsr: return 1; @@ -260,7 +260,7 @@ unsigned Emitter<CodeEmitter>::getMachineOpValue(const MachineInstr &MI, #ifndef NDEBUG cerr << MO; #endif - llvm_unreachable(); + llvm_unreachable(0); } return 0; } @@ -340,7 +340,7 @@ void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI) { NumEmitted++; // Keep track of the # of mi's emitted switch (MI.getDesc().TSFlags & ARMII::FormMask) { default: { - LLVM_UNREACHABLE("Unhandled instruction encoding format!"); + llvm_unreachable("Unhandled instruction encoding format!"); break; } case ARMII::Pseudo: @@ -458,10 +458,10 @@ void Emitter<CodeEmitter>::emitConstPoolInstruction(const MachineInstr &MI) { else if (CFP->getType() == Type::DoubleTy) emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue()); else { - LLVM_UNREACHABLE("Unable to handle this constantpool entry!"); + llvm_unreachable("Unable to handle this constantpool entry!"); } } else { - LLVM_UNREACHABLE("Unable to handle this constantpool entry!"); + llvm_unreachable("Unable to handle this constantpool entry!"); } } } @@ -589,7 +589,7 @@ void Emitter<CodeEmitter>::emitPseudoInstruction(const MachineInstr &MI) { unsigned Opcode = MI.getDesc().Opcode; switch (Opcode) { default: - LLVM_UNREACHABLE("ARMCodeEmitter::emitPseudoInstruction");//FIXME: + llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");//FIXME: case TargetInstrInfo::INLINEASM: { // We allow inline assembler nodes with empty bodies - they can // implicitly define registers, which is ok for JIT. @@ -676,7 +676,7 @@ unsigned Emitter<CodeEmitter>::getMachineSoRegOpValue( // ROR - 0111 // RRX - 0110 and bit[11:8] clear. switch (SOpc) { - default: LLVM_UNREACHABLE("Unknown shift opc!"); + default: llvm_unreachable("Unknown shift opc!"); case ARM_AM::lsl: SBits = 0x1; break; case ARM_AM::lsr: SBits = 0x3; break; case ARM_AM::asr: SBits = 0x5; break; @@ -690,7 +690,7 @@ unsigned Emitter<CodeEmitter>::getMachineSoRegOpValue( // ASR - 100 // ROR - 110 switch (SOpc) { - default: LLVM_UNREACHABLE("Unknown shift opc!"); + default: llvm_unreachable("Unknown shift opc!"); case ARM_AM::lsl: SBits = 0x0; break; case ARM_AM::lsr: SBits = 0x2; break; case ARM_AM::asr: SBits = 0x4; break; @@ -959,7 +959,7 @@ static unsigned getAddrModeUPBits(unsigned Mode) { // DA - Decrement after - bit U = 0 and bit P = 0 // DB - Decrement before - bit U = 0 and bit P = 1 switch (Mode) { - default: LLVM_UNREACHABLE("Unknown addressing sub-mode!"); + default: llvm_unreachable("Unknown addressing sub-mode!"); case ARM_AM::da: break; case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break; case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break; @@ -1123,7 +1123,7 @@ void Emitter<CodeEmitter>::emitBranchInstruction(const MachineInstr &MI) { const TargetInstrDesc &TID = MI.getDesc(); if (TID.Opcode == ARM::TPsoft) { - LLVM_UNREACHABLE("ARM::TPsoft FIXME"); // FIXME + llvm_unreachable("ARM::TPsoft FIXME"); // FIXME } // Part of binary is determined by TableGn. diff --git a/lib/Target/ARM/ARMConstantIslandPass.cpp b/lib/Target/ARM/ARMConstantIslandPass.cpp index 1f2376e..0a160b6 100644 --- a/lib/Target/ARM/ARMConstantIslandPass.cpp +++ b/lib/Target/ARM/ARMConstantIslandPass.cpp @@ -449,7 +449,7 @@ void ARMConstantIslands::InitialFunctionScan(MachineFunction &Fn, Bits = 8; // Taking the address of a CP entry. break; } - LLVM_UNREACHABLE("Unknown addressing mode for CP reference!"); + llvm_unreachable("Unknown addressing mode for CP reference!"); case ARMII::AddrMode1: // AM1: 8 bits << 2 Bits = 8; Scale = 4; // Taking the address of a CP entry. diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 83aa60f..9420d21 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -470,7 +470,7 @@ unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const { /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) { switch (CC) { - default: LLVM_UNREACHABLE("Unknown condition code!"); + default: llvm_unreachable("Unknown condition code!"); case ISD::SETNE: return ARMCC::NE; case ISD::SETEQ: return ARMCC::EQ; case ISD::SETGT: return ARMCC::GT; @@ -492,7 +492,7 @@ static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, bool Invert = false; CondCode2 = ARMCC::AL; switch (CC) { - default: LLVM_UNREACHABLE("Unknown FP condition!"); + default: llvm_unreachable("Unknown FP condition!"); case ISD::SETEQ: case ISD::SETOEQ: CondCode = ARMCC::EQ; break; case ISD::SETGT: @@ -661,7 +661,7 @@ CCAssignFn *ARMTargetLowering::CCAssignFnForNode(unsigned CC, bool Return) const { switch (CC) { default: - LLVM_UNREACHABLE("Unsupported calling convention"); + llvm_unreachable("Unsupported calling convention"); case CallingConv::C: case CallingConv::Fast: // Use target triple & subtarget features to do actual dispatch. @@ -745,7 +745,7 @@ LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall, } switch (VA.getLocInfo()) { - default: LLVM_UNREACHABLE("Unknown loc info!"); + default: llvm_unreachable("Unknown loc info!"); case CCValAssign::Full: break; case CCValAssign::BCvt: Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val); @@ -858,7 +858,7 @@ SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) { // Promote the value if needed. switch (VA.getLocInfo()) { - default: LLVM_UNREACHABLE("Unknown loc info!"); + default: llvm_unreachable("Unknown loc info!"); case CCValAssign::Full: break; case CCValAssign::SExt: Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); @@ -1060,7 +1060,7 @@ SDValue ARMTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) { SDValue Arg = Op.getOperand(realRVLocIdx*2+1); switch (VA.getLocInfo()) { - default: LLVM_UNREACHABLE("Unknown loc info!"); + default: llvm_unreachable("Unknown loc info!"); case CCValAssign::Full: break; case CCValAssign::BCvt: Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg); @@ -1442,7 +1442,7 @@ ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) { // to 32 bits. Insert an assert[sz]ext to capture this, then // truncate to the right size. switch (VA.getLocInfo()) { - default: LLVM_UNREACHABLE("Unknown loc info!"); + default: llvm_unreachable("Unknown loc info!"); case CCValAssign::Full: break; case CCValAssign::BCvt: ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue); @@ -2006,7 +2006,7 @@ static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) { if (Op.getOperand(1).getValueType().isFloatingPoint()) { switch (SetCCOpcode) { - default: LLVM_UNREACHABLE("Illegal FP comparison"); break; + default: llvm_unreachable("Illegal FP comparison"); break; case ISD::SETUNE: case ISD::SETNE: Invert = true; // Fallthrough case ISD::SETOEQ: @@ -2045,7 +2045,7 @@ static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) { } else { // Integer comparisons. switch (SetCCOpcode) { - default: LLVM_UNREACHABLE("Illegal integer comparison"); break; + default: llvm_unreachable("Illegal integer comparison"); break; case ISD::SETNE: Invert = true; case ISD::SETEQ: Opc = ARMISD::VCEQ; break; case ISD::SETLT: Swap = true; @@ -2149,7 +2149,7 @@ static SDValue isVMOVSplat(uint64_t SplatBits, uint64_t SplatUndef, } default: - LLVM_UNREACHABLE("unexpected size for isVMOVSplat"); + llvm_unreachable("unexpected size for isVMOVSplat"); break; } @@ -2191,7 +2191,7 @@ static SDValue BuildSplat(SDValue Val, MVT VT, SelectionDAG &DAG, DebugLoc dl) { case 16: CanonicalVT = MVT::v4i16; break; case 32: CanonicalVT = MVT::v2i32; break; case 64: CanonicalVT = MVT::v1i64; break; - default: LLVM_UNREACHABLE("unexpected splat element type"); break; + default: llvm_unreachable("unexpected splat element type"); break; } } else { assert(VT.is128BitVector() && "unknown splat vector size"); @@ -2200,7 +2200,7 @@ static SDValue BuildSplat(SDValue Val, MVT VT, SelectionDAG &DAG, DebugLoc dl) { case 16: CanonicalVT = MVT::v8i16; break; case 32: CanonicalVT = MVT::v4i32; break; case 64: CanonicalVT = MVT::v2i64; break; - default: LLVM_UNREACHABLE("unexpected splat element type"); break; + default: llvm_unreachable("unexpected splat element type"); break; } } @@ -2260,7 +2260,7 @@ static SDValue LowerCONCAT_VECTORS(SDValue Op) { SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { switch (Op.getOpcode()) { - default: LLVM_UNREACHABLE("Don't know how to custom lower this!"); + default: llvm_unreachable("Don't know how to custom lower this!"); case ISD::ConstantPool: return LowerConstantPool(Op, DAG); case ISD::GlobalAddress: return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) : @@ -2303,7 +2303,7 @@ void ARMTargetLowering::ReplaceNodeResults(SDNode *N, SelectionDAG &DAG) { switch (N->getOpcode()) { default: - LLVM_UNREACHABLE("Don't know how to custom expand this!"); + llvm_unreachable("Don't know how to custom expand this!"); return; case ISD::BIT_CONVERT: Results.push_back(ExpandBIT_CONVERT(N, DAG)); @@ -2595,7 +2595,7 @@ static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) { case Intrinsic::arm_neon_vshiftlu: if (isVShiftLImm(N->getOperand(2), VT, true, Cnt)) break; - LLVM_UNREACHABLE("invalid shift count for vshll intrinsic"); + llvm_unreachable("invalid shift count for vshll intrinsic"); case Intrinsic::arm_neon_vrshifts: case Intrinsic::arm_neon_vrshiftu: @@ -2612,7 +2612,7 @@ static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) { case Intrinsic::arm_neon_vqshiftsu: if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) break; - LLVM_UNREACHABLE("invalid shift count for vqshlu intrinsic"); + llvm_unreachable("invalid shift count for vqshlu intrinsic"); case Intrinsic::arm_neon_vshiftn: case Intrinsic::arm_neon_vrshiftn: @@ -2625,10 +2625,10 @@ static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) { // Narrowing shifts require an immediate right shift. if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt)) break; - LLVM_UNREACHABLE("invalid shift count for narrowing vector shift intrinsic"); + llvm_unreachable("invalid shift count for narrowing vector shift intrinsic"); default: - LLVM_UNREACHABLE("unhandled vector shift"); + llvm_unreachable("unhandled vector shift"); } switch (IntNo) { @@ -2686,7 +2686,7 @@ static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) { else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt)) VShiftOpc = ARMISD::VSRI; else { - LLVM_UNREACHABLE("invalid shift count for vsli/vsri intrinsic"); + llvm_unreachable("invalid shift count for vsli/vsri intrinsic"); } return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0), @@ -2720,7 +2720,7 @@ static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG, int64_t Cnt; switch (N->getOpcode()) { - default: LLVM_UNREACHABLE("unexpected shift opcode"); + default: llvm_unreachable("unexpected shift opcode"); case ISD::SHL: if (isVShiftLImm(N->getOperand(1), VT, false, Cnt)) @@ -2763,7 +2763,7 @@ static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG, unsigned Opc = 0; switch (N->getOpcode()) { - default: LLVM_UNREACHABLE("unexpected opcode"); + default: llvm_unreachable("unexpected opcode"); case ISD::SIGN_EXTEND: Opc = ARMISD::VGETLANEs; break; diff --git a/lib/Target/ARM/ARMJITInfo.cpp b/lib/Target/ARM/ARMJITInfo.cpp index a030a8c..f67bd8c 100644 --- a/lib/Target/ARM/ARMJITInfo.cpp +++ b/lib/Target/ARM/ARMJITInfo.cpp @@ -104,7 +104,7 @@ extern "C" { ); #else // Not an ARM host void ARMCompilationCallback() { - LLVM_UNREACHABLE("Cannot call ARMCompilationCallback() on a non-ARM arch!"); + llvm_unreachable("Cannot call ARMCompilationCallback() on a non-ARM arch!"); } #endif } @@ -123,12 +123,12 @@ extern "C" void ARMCompilationCallbackC(intptr_t StubAddr) { // ldr pc, [pc,#-4] // <addr> if (!sys::Memory::setRangeWritable((void*)StubAddr, 8)) { - LLVM_UNREACHABLE("ERROR: Unable to mark stub writable"); + llvm_unreachable("ERROR: Unable to mark stub writable"); } *(intptr_t *)StubAddr = 0xe51ff004; // ldr pc, [pc, #-4] *(intptr_t *)(StubAddr+4) = NewVal; if (!sys::Memory::setRangeExecutable((void*)StubAddr, 8)) { - LLVM_UNREACHABLE("ERROR: Unable to mark stub executable"); + llvm_unreachable("ERROR: Unable to mark stub executable"); } } diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index 1d62707..13bed95 100644 --- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -138,7 +138,7 @@ static int getLoadStoreMultipleOpcode(int Opcode) { case ARM::FSTD: NumFSTMGened++; return ARM::FSTMD; - default: LLVM_UNREACHABLE("Unhandled opcode!"); + default: llvm_unreachable("Unhandled opcode!"); } return 0; } @@ -513,7 +513,7 @@ static unsigned getPreIndexedLoadStoreOpcode(unsigned Opc) { case ARM::t2STRi8: case ARM::t2STRi12: return ARM::t2STR_PRE; - default: LLVM_UNREACHABLE("Unhandled opcode!"); + default: llvm_unreachable("Unhandled opcode!"); } return 0; } @@ -532,7 +532,7 @@ static unsigned getPostIndexedLoadStoreOpcode(unsigned Opc) { case ARM::t2STRi8: case ARM::t2STRi12: return ARM::t2STR_POST; - default: LLVM_UNREACHABLE("Unhandled opcode!"); + default: llvm_unreachable("Unhandled opcode!"); } return 0; } diff --git a/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp b/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp index 0a55c0c..f878a76 100644 --- a/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp +++ b/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp @@ -211,7 +211,7 @@ bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) { // Print out labels for the function. const Function *F = MF.getFunction(); switch (F->getLinkage()) { - default: LLVM_UNREACHABLE("Unknown linkage type!"); + default: llvm_unreachable("Unknown linkage type!"); case Function::PrivateLinkage: case Function::InternalLinkage: SwitchToTextSection("\t.text", F); @@ -308,7 +308,7 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum, O << TRI->getAsmName(Reg); } } else - LLVM_UNREACHABLE("not implemented"); + llvm_unreachable("not implemented"); break; } case MachineOperand::MO_Immediate: { @@ -1139,7 +1139,7 @@ void ARMAsmPrinter::printModuleLevelGV(const GlobalVariable* GVar) { case GlobalValue::InternalLinkage: break; default: - LLVM_UNREACHABLE("Unknown linkage type!"); + llvm_unreachable("Unknown linkage type!"); } EmitAlignment(Align, GVar); diff --git a/lib/Target/ARM/Thumb1RegisterInfo.cpp b/lib/Target/ARM/Thumb1RegisterInfo.cpp index 940eea4..9c544e3 100644 --- a/lib/Target/ARM/Thumb1RegisterInfo.cpp +++ b/lib/Target/ARM/Thumb1RegisterInfo.cpp @@ -511,7 +511,7 @@ void Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, break; } default: - LLVM_UNREACHABLE("Unsupported addressing mode!"); + llvm_unreachable("Unsupported addressing mode!"); break; } diff --git a/lib/Target/Alpha/AlphaCodeEmitter.cpp b/lib/Target/Alpha/AlphaCodeEmitter.cpp index 9a7c5a4..98eeb89 100644 --- a/lib/Target/Alpha/AlphaCodeEmitter.cpp +++ b/lib/Target/Alpha/AlphaCodeEmitter.cpp @@ -166,7 +166,7 @@ static unsigned getAlphaRegNumber(unsigned Reg) { case Alpha::R30 : case Alpha::F30 : return 30; case Alpha::R31 : case Alpha::F31 : return 31; default: - LLVM_UNREACHABLE("Unhandled reg"); + llvm_unreachable("Unhandled reg"); } } @@ -217,7 +217,7 @@ unsigned AlphaCodeEmitter::getMachineOpValue(const MachineInstr &MI, Offset = MI.getOperand(3).getImm(); break; default: - LLVM_UNREACHABLE("unknown relocatable instruction"); + llvm_unreachable("unknown relocatable instruction"); } if (MO.isGlobal()) MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), @@ -238,7 +238,7 @@ unsigned AlphaCodeEmitter::getMachineOpValue(const MachineInstr &MI, #ifndef NDEBUG cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n"; #endif - llvm_unreachable(); + llvm_unreachable(0); } return rv; diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp index 977e621..0f4d0f4 100644 --- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp +++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp @@ -338,7 +338,7 @@ SDNode *AlphaDAGToDAGISel::Select(SDValue Op) { bool rev = false; bool inv = false; switch(CC) { - default: DEBUG(N->dump(CurDAG)); LLVM_UNREACHABLE("Unknown FP comparison!"); + default: DEBUG(N->dump(CurDAG)); llvm_unreachable("Unknown FP comparison!"); case ISD::SETEQ: case ISD::SETOEQ: case ISD::SETUEQ: Opc = Alpha::CMPTEQ; break; case ISD::SETLT: case ISD::SETOLT: case ISD::SETULT: @@ -472,7 +472,7 @@ void AlphaDAGToDAGISel::SelectCALL(SDValue Op) { } else if (TypeOperands[i] == MVT::f64) { Opc = Alpha::STT; } else - LLVM_UNREACHABLE("Unknown operand"); + llvm_unreachable("Unknown operand"); SDValue Ops[] = { CallOperands[i], getI64Imm((i - 6) * 8), CurDAG->getCopyFromReg(Chain, dl, Alpha::R30, MVT::i64), @@ -489,7 +489,7 @@ void AlphaDAGToDAGISel::SelectCALL(SDValue Op) { CallOperands[i], InFlag); InFlag = Chain.getValue(1); } else - LLVM_UNREACHABLE("Unknown operand"); + llvm_unreachable("Unknown operand"); } // Finally, once everything is in registers to pass to the call, emit the @@ -512,7 +512,7 @@ void AlphaDAGToDAGISel::SelectCALL(SDValue Op) { std::vector<SDValue> CallResults; switch (N->getValueType(0).getSimpleVT()) { - default: LLVM_UNREACHABLE("Unexpected ret value!"); + default: llvm_unreachable("Unexpected ret value!"); case MVT::Other: break; case MVT::i64: Chain = CurDAG->getCopyFromReg(Chain, dl, diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp index 2893536..9097a8a 100644 --- a/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/lib/Target/Alpha/AlphaISelLowering.cpp @@ -314,7 +314,7 @@ static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) { SDValue()); switch (Op.getNumOperands()) { default: - LLVM_UNREACHABLE("Do not know how to return this many arguments!"); + llvm_unreachable("Do not know how to return this many arguments!"); case 1: break; //return SDValue(); // ret void is legal @@ -380,7 +380,7 @@ AlphaTargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, for (unsigned i = 0, e = Args.size(); i != e; ++i) { switch (getValueType(Args[i].Ty).getSimpleVT()) { - default: LLVM_UNREACHABLE("Unexpected ValueType for argument!"); + default: llvm_unreachable("Unexpected ValueType for argument!"); case MVT::i1: case MVT::i8: case MVT::i16: @@ -476,7 +476,7 @@ void AlphaTargetLowering::LowerVAARG(SDNode *N, SDValue &Chain, SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { DebugLoc dl = Op.getDebugLoc(); switch (Op.getOpcode()) { - default: LLVM_UNREACHABLE("Wasn't expecting to be able to lower this!"); + default: llvm_unreachable("Wasn't expecting to be able to lower this!"); case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsBase, VarArgsOffset); @@ -527,7 +527,7 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { return Lo; } case ISD::GlobalTLSAddress: - LLVM_UNREACHABLE("TLS not implemented for Alpha."); + llvm_unreachable("TLS not implemented for Alpha."); case ISD::GlobalAddress: { GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); GlobalValue *GV = GSDN->getGlobal(); diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp index 139a4db..3cb2ce3 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.cpp +++ b/lib/Target/Alpha/AlphaInstrInfo.cpp @@ -201,7 +201,7 @@ AlphaInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, .addReg(SrcReg, getKillRegState(isKill)) .addFrameIndex(FrameIdx).addReg(Alpha::F31); else - LLVM_UNREACHABLE("Unhandled register class"); + llvm_unreachable("Unhandled register class"); } void AlphaInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, @@ -217,7 +217,7 @@ void AlphaInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, else if (RC == Alpha::GPRCRegisterClass) Opc = Alpha::STQ; else - LLVM_UNREACHABLE("Unhandled register class"); + llvm_unreachable("Unhandled register class"); DebugLoc DL = DebugLoc::getUnknownLoc(); MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)); @@ -246,7 +246,7 @@ AlphaInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, BuildMI(MBB, MI, DL, get(Alpha::LDQ), DestReg) .addFrameIndex(FrameIdx).addReg(Alpha::F31); else - LLVM_UNREACHABLE("Unhandled register class"); + llvm_unreachable("Unhandled register class"); } void AlphaInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, @@ -261,7 +261,7 @@ void AlphaInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, else if (RC == Alpha::GPRCRegisterClass) Opc = Alpha::LDQ; else - LLVM_UNREACHABLE("Unhandled register class"); + llvm_unreachable("Unhandled register class"); DebugLoc DL = DebugLoc::getUnknownLoc(); MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); @@ -332,7 +332,7 @@ static unsigned AlphaRevCondCode(unsigned Opcode) { case Alpha::FBLE: return Alpha::FBGT; case Alpha::FBLT: return Alpha::FBGE; default: - LLVM_UNREACHABLE("Unknown opcode"); + llvm_unreachable("Unknown opcode"); } return 0; // Not reached } diff --git a/lib/Target/Alpha/AlphaJITInfo.cpp b/lib/Target/Alpha/AlphaJITInfo.cpp index 8919dc0..4feb277 100644 --- a/lib/Target/Alpha/AlphaJITInfo.cpp +++ b/lib/Target/Alpha/AlphaJITInfo.cpp @@ -72,7 +72,7 @@ static void EmitBranchToAt(void *At, void *To) { void AlphaJITInfo::replaceMachineCodeForFunction(void *Old, void *New) { //FIXME - llvm_unreachable(); + llvm_unreachable(0); } static TargetJITInfo::JITCompilerFn JITCompilerFunction; @@ -185,7 +185,7 @@ extern "C" { ); #else void AlphaCompilationCallback() { - LLVM_UNREACHABLE("Cannot call AlphaCompilationCallback() on a non-Alpha arch!"); + llvm_unreachable("Cannot call AlphaCompilationCallback() on a non-Alpha arch!"); } #endif } @@ -241,7 +241,7 @@ void AlphaJITInfo::relocate(void *Function, MachineRelocation *MR, long idx = 0; bool doCommon = true; switch ((Alpha::RelocationType)MR->getRelocationType()) { - default: LLVM_UNREACHABLE("Unknown relocation type!"); + default: llvm_unreachable("Unknown relocation type!"); case Alpha::reloc_literal: //This is a LDQl idx = MR->getGOTIndex(); @@ -281,7 +281,7 @@ void AlphaJITInfo::relocate(void *Function, MachineRelocation *MR, DOUT << "LDA: " << idx << "\n"; break; default: - LLVM_UNREACHABLE("Cannot handle gpdist yet"); + llvm_unreachable("Cannot handle gpdist yet"); } break; case Alpha::reloc_bsr: { diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp index f1e651c..0c4a36a 100644 --- a/lib/Target/Alpha/AlphaRegisterInfo.cpp +++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp @@ -307,7 +307,7 @@ void AlphaRegisterInfo::emitEpilogue(MachineFunction &MF, } unsigned AlphaRegisterInfo::getRARegister() const { - LLVM_UNREACHABLE("What is the return address register"); + llvm_unreachable("What is the return address register"); return 0; } @@ -316,17 +316,17 @@ unsigned AlphaRegisterInfo::getFrameRegister(MachineFunction &MF) const { } unsigned AlphaRegisterInfo::getEHExceptionRegister() const { - LLVM_UNREACHABLE("What is the exception register"); + llvm_unreachable("What is the exception register"); return 0; } unsigned AlphaRegisterInfo::getEHHandlerRegister() const { - LLVM_UNREACHABLE("What is the exception handler register"); + llvm_unreachable("What is the exception handler register"); return 0; } int AlphaRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { - LLVM_UNREACHABLE("What is the dwarf register number"); + llvm_unreachable("What is the dwarf register number"); return -1; } diff --git a/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp b/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp index 38bdeb2..1e3e83c 100644 --- a/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp +++ b/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp @@ -101,7 +101,7 @@ void AlphaAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) { return; case MachineOperand::MO_Immediate: - LLVM_UNREACHABLE("printOp() does not handle immediate values"); + llvm_unreachable("printOp() does not handle immediate values"); return; case MachineOperand::MO_MachineBasicBlock: @@ -155,7 +155,7 @@ bool AlphaAsmPrinter::runOnMachineFunction(MachineFunction &MF) { EmitAlignment(MF.getAlignment(), F); switch (F->getLinkage()) { - default: LLVM_UNREACHABLE("Unknown linkage type!"); + default: llvm_unreachable("Unknown linkage type!"); case Function::InternalLinkage: // Symbols default to internal. case Function::PrivateLinkage: break; @@ -188,7 +188,7 @@ bool AlphaAsmPrinter::runOnMachineFunction(MachineFunction &MF) { // Print the assembly for the instruction. ++EmittedInsts; if (!printInstruction(II)) { - LLVM_UNREACHABLE("Unhandled instruction in asm writer!"); + llvm_unreachable("Unhandled instruction in asm writer!"); } } } @@ -248,7 +248,7 @@ void AlphaAsmPrinter::printModuleLevelGV(const GlobalVariable* GVar) { case GlobalValue::PrivateLinkage: break; default: - LLVM_UNREACHABLE("Unknown linkage type!"); + llvm_unreachable("Unknown linkage type!"); } // 3: Type, Size, Align diff --git a/lib/Target/CBackend/CBackend.cpp b/lib/Target/CBackend/CBackend.cpp index c3c2b0e..09ff9a2 100644 --- a/lib/Target/CBackend/CBackend.cpp +++ b/lib/Target/CBackend/CBackend.cpp @@ -289,11 +289,11 @@ namespace { void visitBranchInst(BranchInst &I); void visitSwitchInst(SwitchInst &I); void visitInvokeInst(InvokeInst &I) { - LLVM_UNREACHABLE("Lowerinvoke pass didn't work!"); + llvm_unreachable("Lowerinvoke pass didn't work!"); } void visitUnwindInst(UnwindInst &I) { - LLVM_UNREACHABLE("Lowerinvoke pass didn't work!"); + llvm_unreachable("Lowerinvoke pass didn't work!"); } void visitUnreachableInst(UnreachableInst &I); @@ -327,7 +327,7 @@ namespace { #ifndef NDEBUG cerr << "C Writer does not know about " << I; #endif - llvm_unreachable(); + llvm_unreachable(0); } void outputLValue(Instruction *I) { @@ -513,7 +513,7 @@ CWriter::printSimpleType(raw_ostream &Out, const Type *Ty, bool isSigned, #ifndef NDEBUG cerr << "Unknown primitive type: " << *Ty << "\n"; #endif - llvm_unreachable(); + llvm_unreachable(0); } } @@ -560,7 +560,7 @@ CWriter::printSimpleType(std::ostream &Out, const Type *Ty, bool isSigned, #ifndef NDEBUG cerr << "Unknown primitive type: " << *Ty << "\n"; #endif - llvm_unreachable(); + llvm_unreachable(0); } } @@ -661,7 +661,7 @@ raw_ostream &CWriter::printType(raw_ostream &Out, const Type *Ty, return Out << TyName << ' ' << NameSoFar; } default: - LLVM_UNREACHABLE("Unhandled case in getTypeProps!"); + llvm_unreachable("Unhandled case in getTypeProps!"); } return Out; @@ -764,7 +764,7 @@ std::ostream &CWriter::printType(std::ostream &Out, const Type *Ty, return Out << TyName << ' ' << NameSoFar; } default: - LLVM_UNREACHABLE("Unhandled case in getTypeProps!"); + llvm_unreachable("Unhandled case in getTypeProps!"); } return Out; @@ -923,7 +923,7 @@ void CWriter::printCast(unsigned opc, const Type *SrcTy, const Type *DstTy) { Out << ')'; break; default: - LLVM_UNREACHABLE("Invalid cast opcode"); + llvm_unreachable("Invalid cast opcode"); } // Print the source type cast @@ -953,7 +953,7 @@ void CWriter::printCast(unsigned opc, const Type *SrcTy, const Type *DstTy) { case Instruction::FPToUI: break; // These don't need a source cast. default: - LLVM_UNREACHABLE("Invalid cast opcode"); + llvm_unreachable("Invalid cast opcode"); break; } } @@ -1062,10 +1062,10 @@ void CWriter::printConstant(Constant *CPV, bool Static) { case ICmpInst::ICMP_UGT: Out << " > "; break; case ICmpInst::ICMP_SGE: case ICmpInst::ICMP_UGE: Out << " >= "; break; - default: LLVM_UNREACHABLE("Illegal ICmp predicate"); + default: llvm_unreachable("Illegal ICmp predicate"); } break; - default: LLVM_UNREACHABLE("Illegal opcode here!"); + default: llvm_unreachable("Illegal opcode here!"); } printConstantWithCast(CE->getOperand(1), CE->getOpcode()); if (NeedsClosingParens) @@ -1083,7 +1083,7 @@ void CWriter::printConstant(Constant *CPV, bool Static) { else { const char* op = 0; switch (CE->getPredicate()) { - default: LLVM_UNREACHABLE("Illegal FCmp predicate"); + default: llvm_unreachable("Illegal FCmp predicate"); case FCmpInst::FCMP_ORD: op = "ord"; break; case FCmpInst::FCMP_UNO: op = "uno"; break; case FCmpInst::FCMP_UEQ: op = "ueq"; break; @@ -1115,7 +1115,7 @@ void CWriter::printConstant(Constant *CPV, bool Static) { cerr << "CWriter Error: Unhandled constant expression: " << *CE << "\n"; #endif - llvm_unreachable(); + llvm_unreachable(0); } } else if (isa<UndefValue>(CPV) && CPV->getType()->isSingleValueType()) { Out << "(("; @@ -1324,7 +1324,7 @@ void CWriter::printConstant(Constant *CPV, bool Static) { #ifndef NDEBUG cerr << "Unknown constant type: " << *CPV << "\n"; #endif - llvm_unreachable(); + llvm_unreachable(0); } } @@ -2128,7 +2128,7 @@ void CWriter::printFloatingPointConstants(const Constant *C) { << "}; /* Long double constant */\n"; } else { - LLVM_UNREACHABLE("Unknown float type!"); + llvm_unreachable("Unknown float type!"); } } @@ -2680,7 +2680,7 @@ void CWriter::visitBinaryOperator(Instruction &I) { #ifndef NDEBUG cerr << "Invalid operator type!" << I; #endif - llvm_unreachable(); + llvm_unreachable(0); } writeOperandWithCast(I.getOperand(1), I.getOpcode()); @@ -2721,7 +2721,7 @@ void CWriter::visitICmpInst(ICmpInst &I) { #ifndef NDEBUG cerr << "Invalid icmp predicate!" << I; #endif - llvm_unreachable(); + llvm_unreachable(0); } writeOperandWithCast(I.getOperand(1), I); @@ -2745,7 +2745,7 @@ void CWriter::visitFCmpInst(FCmpInst &I) { const char* op = 0; switch (I.getPredicate()) { - default: LLVM_UNREACHABLE("Illegal FCmp predicate"); + default: llvm_unreachable("Illegal FCmp predicate"); case FCmpInst::FCMP_ORD: op = "ord"; break; case FCmpInst::FCMP_UNO: op = "uno"; break; case FCmpInst::FCMP_UEQ: op = "ueq"; break; @@ -2773,7 +2773,7 @@ void CWriter::visitFCmpInst(FCmpInst &I) { static const char * getFloatBitCastField(const Type *Ty) { switch (Ty->getTypeID()) { - default: LLVM_UNREACHABLE("Invalid Type"); + default: llvm_unreachable("Invalid Type"); case Type::FloatTyID: return "Float"; case Type::DoubleTyID: return "Double"; case Type::IntegerTyID: { @@ -3136,7 +3136,7 @@ bool CWriter::visitBuiltinCall(CallInst &I, Intrinsic::ID ID, Out << ')'; // Multiple GCC builtins multiplex onto this intrinsic. switch (cast<ConstantInt>(I.getOperand(3))->getZExtValue()) { - default: LLVM_UNREACHABLE("Invalid llvm.x86.sse.cmp!"); + default: llvm_unreachable("Invalid llvm.x86.sse.cmp!"); case 0: Out << "__builtin_ia32_cmpeq"; break; case 1: Out << "__builtin_ia32_cmplt"; break; case 2: Out << "__builtin_ia32_cmple"; break; @@ -3348,7 +3348,7 @@ void CWriter::visitInlineAsm(CallInst &CI) { } void CWriter::visitMallocInst(MallocInst &I) { - LLVM_UNREACHABLE("lowerallocations pass didn't work!"); + llvm_unreachable("lowerallocations pass didn't work!"); } void CWriter::visitAllocaInst(AllocaInst &I) { @@ -3365,7 +3365,7 @@ void CWriter::visitAllocaInst(AllocaInst &I) { } void CWriter::visitFreeInst(FreeInst &I) { - LLVM_UNREACHABLE("lowerallocations pass didn't work!"); + llvm_unreachable("lowerallocations pass didn't work!"); } void CWriter::printGEPExpression(Value *Ptr, gep_type_iterator I, diff --git a/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp b/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp index 77e66c8..bc4facd 100644 --- a/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp +++ b/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp @@ -265,7 +265,7 @@ namespace { && "Invalid negated immediate rotate 7-bit argument"); O << -value; } else { - LLVM_UNREACHABLE("Invalid/non-immediate rotate amount in printRotateNeg7Imm"); + llvm_unreachable("Invalid/non-immediate rotate amount in printRotateNeg7Imm"); } } @@ -276,7 +276,7 @@ namespace { && "Invalid negated immediate rotate 7-bit argument"); O << -value; } else { - LLVM_UNREACHABLE("Invalid/non-immediate rotate amount in printRotateNeg7Imm"); + llvm_unreachable("Invalid/non-immediate rotate amount in printRotateNeg7Imm"); } } @@ -434,7 +434,7 @@ LinuxAsmPrinter::runOnMachineFunction(MachineFunction &MF) EmitAlignment(MF.getAlignment(), F); switch (F->getLinkage()) { - default: LLVM_UNREACHABLE("Unknown linkage type!"); + default: llvm_unreachable("Unknown linkage type!"); case Function::PrivateLinkage: case Function::InternalLinkage: // Symbols default to internal. break; diff --git a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp index ddb9a36..8f704ec 100644 --- a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp +++ b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp @@ -378,7 +378,7 @@ namespace { break; case 'v': // not offsetable #if 1 - LLVM_UNREACHABLE("InlineAsmMemoryOperand 'v' constraint not handled."); + llvm_unreachable("InlineAsmMemoryOperand 'v' constraint not handled."); #else SelectAddrIdxOnly(Op, Op, Op0, Op1); #endif diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp index 6b9df67..2042a93 100644 --- a/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/lib/Target/CellSPU/SPUISelLowering.cpp @@ -875,7 +875,7 @@ LowerConstantPool(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { } } - LLVM_UNREACHABLE("LowerConstantPool: Relocation model other than static" + llvm_unreachable("LowerConstantPool: Relocation model other than static" " not supported."); return SDValue(); } @@ -906,7 +906,7 @@ LowerJumpTable(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { } } - LLVM_UNREACHABLE("LowerJumpTable: Relocation model other than static" + llvm_unreachable("LowerJumpTable: Relocation model other than static" " not supported."); return SDValue(); } @@ -1138,7 +1138,7 @@ LowerCALL(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); switch (Arg.getValueType().getSimpleVT()) { - default: LLVM_UNREACHABLE("Unexpected ValueType for argument!"); + default: llvm_unreachable("Unexpected ValueType for argument!"); case MVT::i8: case MVT::i16: case MVT::i32: @@ -1270,7 +1270,7 @@ LowerCALL(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { // If the call has results, copy the values out of the ret val registers. switch (TheCall->getValueType(0).getSimpleVT()) { - default: LLVM_UNREACHABLE("Unexpected ret value!"); + default: llvm_unreachable("Unexpected ret value!"); case MVT::Other: break; case MVT::i32: if (TheCall->getValueType(1) == MVT::i32) { @@ -1738,7 +1738,7 @@ static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { } else if (EltVT == MVT::i64 || EltVT == MVT::f64) { V2EltIdx0 = 2; } else - LLVM_UNREACHABLE("Unhandled vector type in LowerVECTOR_SHUFFLE"); + llvm_unreachable("Unhandled vector type in LowerVECTOR_SHUFFLE"); for (unsigned i = 0; i != MaxElts; ++i) { if (SVN->getMaskElt(i) < 0) @@ -1834,7 +1834,7 @@ static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) { // Create a constant vector: switch (Op.getValueType().getSimpleVT()) { - default: LLVM_UNREACHABLE("Unexpected constant value type in " + default: llvm_unreachable("Unexpected constant value type in " "LowerSCALAR_TO_VECTOR"); case MVT::v16i8: n_copies = 16; VT = MVT::i8; break; case MVT::v8i16: n_copies = 8; VT = MVT::i16; break; @@ -1853,7 +1853,7 @@ static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) { } else { // Otherwise, copy the value from one register to another: switch (Op0.getValueType().getSimpleVT()) { - default: LLVM_UNREACHABLE("Unexpected value type in LowerSCALAR_TO_VECTOR"); + default: llvm_unreachable("Unexpected value type in LowerSCALAR_TO_VECTOR"); case MVT::i8: case MVT::i16: case MVT::i32: @@ -1880,13 +1880,13 @@ static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { // sanity checks: if (VT == MVT::i8 && EltNo >= 16) - LLVM_UNREACHABLE("SPU LowerEXTRACT_VECTOR_ELT: i8 extraction slot > 15"); + llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i8 extraction slot > 15"); else if (VT == MVT::i16 && EltNo >= 8) - LLVM_UNREACHABLE("SPU LowerEXTRACT_VECTOR_ELT: i16 extraction slot > 7"); + llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i16 extraction slot > 7"); else if (VT == MVT::i32 && EltNo >= 4) - LLVM_UNREACHABLE("SPU LowerEXTRACT_VECTOR_ELT: i32 extraction slot > 4"); + llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i32 extraction slot > 4"); else if (VT == MVT::i64 && EltNo >= 2) - LLVM_UNREACHABLE("SPU LowerEXTRACT_VECTOR_ELT: i64 extraction slot > 2"); + llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i64 extraction slot > 2"); if (EltNo == 0 && (VT == MVT::i32 || VT == MVT::i64)) { // i32 and i64: Element 0 is the preferred slot @@ -2065,7 +2065,7 @@ static SDValue LowerI8Math(SDValue Op, SelectionDAG &DAG, unsigned Opc, assert(Op.getValueType() == MVT::i8); switch (Opc) { default: - LLVM_UNREACHABLE("Unhandled i8 math operator"); + llvm_unreachable("Unhandled i8 math operator"); /*NOTREACHED*/ break; case ISD::ADD: { @@ -2585,7 +2585,7 @@ SPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) cerr << "*Op.getNode():\n"; Op.getNode()->dump(); #endif - llvm_unreachable(); + llvm_unreachable(0); } case ISD::LOAD: case ISD::EXTLOAD: diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp index eba1ca1..26a4241 100644 --- a/lib/Target/CellSPU/SPUInstrInfo.cpp +++ b/lib/Target/CellSPU/SPUInstrInfo.cpp @@ -314,7 +314,7 @@ SPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, } else if (RC == SPU::VECREGRegisterClass) { opc = (isValidFrameIdx) ? SPU::STQDv16i8 : SPU::STQXv16i8; } else { - LLVM_UNREACHABLE("Unknown regclass!"); + llvm_unreachable("Unknown regclass!"); } DebugLoc DL = DebugLoc::getUnknownLoc(); @@ -347,7 +347,7 @@ void SPUInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, } else if (RC == SPU::VECREGRegisterClass) { /* Opc = PPC::STVX; */ } else { - LLVM_UNREACHABLE("Unknown regclass!"); + llvm_unreachable("Unknown regclass!"); } DebugLoc DL = DebugLoc::getUnknownLoc(); MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)) @@ -383,7 +383,7 @@ SPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, } else if (RC == SPU::VECREGRegisterClass) { opc = (isValidFrameIdx) ? SPU::LQDv16i8 : SPU::LQXv16i8; } else { - LLVM_UNREACHABLE("Unknown regclass in loadRegFromStackSlot!"); + llvm_unreachable("Unknown regclass in loadRegFromStackSlot!"); } DebugLoc DL = DebugLoc::getUnknownLoc(); @@ -420,7 +420,7 @@ void SPUInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, } else if (RC == SPU::GPRCRegisterClass) { /* Opc = something else! */ } else { - LLVM_UNREACHABLE("Unknown regclass!"); + llvm_unreachable("Unknown regclass!"); } DebugLoc DL = DebugLoc::getUnknownLoc(); MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); diff --git a/lib/Target/CppBackend/CPPBackend.cpp b/lib/Target/CppBackend/CPPBackend.cpp index 162e9fd..9ebbf00 100644 --- a/lib/Target/CppBackend/CPPBackend.cpp +++ b/lib/Target/CppBackend/CPPBackend.cpp @@ -325,7 +325,7 @@ namespace { void CppWriter::printVisibilityType(GlobalValue::VisibilityTypes VisType) { switch (VisType) { - default: LLVM_UNREACHABLE("Unknown GVar visibility"); + default: llvm_unreachable("Unknown GVar visibility"); case GlobalValue::DefaultVisibility: Out << "GlobalValue::DefaultVisibility"; break; @@ -844,7 +844,7 @@ namespace { printConstant(CE->getOperand(0)); Out << "Constant* " << constName << " = ConstantExpr::getCast("; switch (CE->getOpcode()) { - default: LLVM_UNREACHABLE("Invalid cast opcode"); + default: llvm_unreachable("Invalid cast opcode"); case Instruction::Trunc: Out << "Instruction::Trunc"; break; case Instruction::ZExt: Out << "Instruction::ZExt"; break; case Instruction::SExt: Out << "Instruction::SExt"; break; diff --git a/lib/Target/DarwinTargetAsmInfo.cpp b/lib/Target/DarwinTargetAsmInfo.cpp index 6094976..0b6babe 100644 --- a/lib/Target/DarwinTargetAsmInfo.cpp +++ b/lib/Target/DarwinTargetAsmInfo.cpp @@ -152,7 +152,7 @@ DarwinTargetAsmInfo::SelectSectionForGlobal(const GlobalValue *GV) const { ConstDataCoalSection: MergeableConstSection(cast<GlobalVariable>(GV))); default: - LLVM_UNREACHABLE("Unsuported section kind for global"); + llvm_unreachable("Unsuported section kind for global"); } // FIXME: Do we have any extra special weird cases? @@ -212,6 +212,6 @@ DarwinTargetAsmInfo::SelectSectionForMachineConst(const Type *Ty) const { std::string DarwinTargetAsmInfo::UniqueSectionForGlobal(const GlobalValue* GV, SectionKind::Kind kind) const { - LLVM_UNREACHABLE("Darwin does not use unique sections"); + llvm_unreachable("Darwin does not use unique sections"); return ""; } diff --git a/lib/Target/ELFTargetAsmInfo.cpp b/lib/Target/ELFTargetAsmInfo.cpp index b513a60..752f475 100644 --- a/lib/Target/ELFTargetAsmInfo.cpp +++ b/lib/Target/ELFTargetAsmInfo.cpp @@ -75,7 +75,7 @@ ELFTargetAsmInfo::SelectSectionForGlobal(const GlobalValue *GV) const { if (const Function *F = dyn_cast<Function>(GV)) { switch (F->getLinkage()) { - default: LLVM_UNREACHABLE("Unknown linkage type!"); + default: llvm_unreachable("Unknown linkage type!"); case Function::PrivateLinkage: case Function::InternalLinkage: case Function::DLLExportLinkage: @@ -124,11 +124,11 @@ ELFTargetAsmInfo::SelectSectionForGlobal(const GlobalValue *GV) const { case SectionKind::ThreadBSS: return TLSBSSSection; default: - LLVM_UNREACHABLE("Unsuported section kind for global"); + llvm_unreachable("Unsuported section kind for global"); } } } else - LLVM_UNREACHABLE("Unsupported global"); + llvm_unreachable("Unsupported global"); return NULL; } diff --git a/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp b/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp index 111749e..e7ed64e 100644 --- a/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp +++ b/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp @@ -318,13 +318,13 @@ void IA64AsmPrinter::printModuleLevelGV(const GlobalVariable* GVar) { case GlobalValue::PrivateLinkage: break; case GlobalValue::GhostLinkage: - LLVM_UNREACHABLE("GhostLinkage cannot appear in IA64AsmPrinter!"); + llvm_unreachable("GhostLinkage cannot appear in IA64AsmPrinter!"); case GlobalValue::DLLImportLinkage: - LLVM_UNREACHABLE("DLLImport linkage is not supported by this target!"); + llvm_unreachable("DLLImport linkage is not supported by this target!"); case GlobalValue::DLLExportLinkage: - LLVM_UNREACHABLE("DLLExport linkage is not supported by this target!"); + llvm_unreachable("DLLExport linkage is not supported by this target!"); default: - LLVM_UNREACHABLE("Unknown linkage type!"); + llvm_unreachable("Unknown linkage type!"); } EmitAlignment(Align, GVar); diff --git a/lib/Target/IA64/IA64ISelDAGToDAG.cpp b/lib/Target/IA64/IA64ISelDAGToDAG.cpp index adb4c4b..fc24241 100644 --- a/lib/Target/IA64/IA64ISelDAGToDAG.cpp +++ b/lib/Target/IA64/IA64ISelDAGToDAG.cpp @@ -215,7 +215,7 @@ SDNode *IA64DAGToDAGISel::SelectDIV(SDValue Op) { if(isFP) { // if this is an FP divide, we finish up here and exit early if(isModulus) - LLVM_UNREACHABLE("Sorry, try another FORTRAN compiler."); + llvm_unreachable("Sorry, try another FORTRAN compiler."); SDValue TmpE2, TmpY3, TmpQ0, TmpR0; @@ -406,7 +406,7 @@ SDNode *IA64DAGToDAGISel::Select(SDValue Op) { APFloat(+1.0f) : APFloat(+1.0))) { V = CurDAG->getCopyFromReg(Chain, dl, IA64::F1, MVT::f64); } else - LLVM_UNREACHABLE("Unexpected FP constant!"); + llvm_unreachable("Unexpected FP constant!"); ReplaceUses(SDValue(N, 0), V); return 0; @@ -468,7 +468,7 @@ SDNode *IA64DAGToDAGISel::Select(SDValue Op) { #ifndef NDEBUG N->dump(CurDAG); #endif - LLVM_UNREACHABLE("Cannot load this type!"); + llvm_unreachable("Cannot load this type!"); case MVT::i1: { // this is a bool Opc = IA64::LD1; // first we load a byte, then compare for != 0 if(N->getValueType(0) == MVT::i1) { // XXX: early exit! @@ -504,7 +504,7 @@ SDNode *IA64DAGToDAGISel::Select(SDValue Op) { unsigned Opc; if (ISD::isNON_TRUNCStore(N)) { switch (N->getOperand(1).getValueType().getSimpleVT()) { - default: LLVM_UNREACHABLE("unknown type in store"); + default: llvm_unreachable("unknown type in store"); case MVT::i1: { // this is a bool Opc = IA64::ST1; // we store either 0 or 1 as a byte // first load zero! @@ -524,7 +524,7 @@ SDNode *IA64DAGToDAGISel::Select(SDValue Op) { } } else { // Truncating store switch(ST->getMemoryVT().getSimpleVT()) { - default: LLVM_UNREACHABLE("unknown type in truncstore"); + default: llvm_unreachable("unknown type in truncstore"); case MVT::i8: Opc = IA64::ST1; break; case MVT::i16: Opc = IA64::ST2; break; case MVT::i32: Opc = IA64::ST4; break; diff --git a/lib/Target/IA64/IA64ISelLowering.cpp b/lib/Target/IA64/IA64ISelLowering.cpp index 8e675eb..587860c 100644 --- a/lib/Target/IA64/IA64ISelLowering.cpp +++ b/lib/Target/IA64/IA64ISelLowering.cpp @@ -194,7 +194,7 @@ void IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG, switch (getValueType(I->getType()).getSimpleVT()) { default: - LLVM_UNREACHABLE("ERROR in LowerArgs: can't lower this type of arg."); + llvm_unreachable("ERROR in LowerArgs: can't lower this type of arg."); case MVT::f32: // fixme? (well, will need to for weird FP structy stuff, // see intel ABI docs) @@ -298,7 +298,7 @@ void IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG, // Finally, inform the code generator which regs we return values in. // (see the ISD::RET: case in the instruction selector) switch (getValueType(F.getReturnType()).getSimpleVT()) { - default: LLVM_UNREACHABLE("i have no idea where to return this type!"); + default: llvm_unreachable("i have no idea where to return this type!"); case MVT::isVoid: break; case MVT::i1: case MVT::i8: @@ -362,7 +362,7 @@ IA64TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, SDValue ValToStore(0, 0), ValToConvert(0, 0); unsigned ObjSize=8; switch (ObjectVT.getSimpleVT()) { - default: LLVM_UNREACHABLE("unexpected argument type!"); + default: llvm_unreachable("unexpected argument type!"); case MVT::i1: case MVT::i8: case MVT::i16: @@ -493,7 +493,7 @@ IA64TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, if (InFlag.getNode()) CallOperands.push_back(InFlag); else - LLVM_UNREACHABLE("this should never happen!"); + llvm_unreachable("this should never happen!"); // to make way for a hack: Chain = DAG.getNode(IA64ISD::BRCALL, dl, NodeTys, @@ -516,7 +516,7 @@ IA64TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, SDValue RetVal; if (RetTyVT != MVT::isVoid) { switch (RetTyVT.getSimpleVT()) { - default: LLVM_UNREACHABLE("Unknown value type to return!"); + default: llvm_unreachable("Unknown value type to return!"); case MVT::i1: { // bools are just like other integers (returned in r8) // we *could* fall through to the truncate below, but this saves a // few redundant predicate ops @@ -573,15 +573,15 @@ SDValue IA64TargetLowering:: LowerOperation(SDValue Op, SelectionDAG &DAG) { DebugLoc dl = Op.getDebugLoc(); switch (Op.getOpcode()) { - default: LLVM_UNREACHABLE("Should not custom lower this!"); + default: llvm_unreachable("Should not custom lower this!"); case ISD::GlobalTLSAddress: - LLVM_UNREACHABLE("TLS not implemented for IA64."); + llvm_unreachable("TLS not implemented for IA64."); case ISD::RET: { SDValue AR_PFSVal, Copy; switch(Op.getNumOperands()) { default: - LLVM_UNREACHABLE("Do not know how to return this many arguments!"); + llvm_unreachable("Do not know how to return this many arguments!"); case 1: AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), dl, VirtGPR, MVT::i64); AR_PFSVal = DAG.getCopyToReg(AR_PFSVal.getValue(1), dl, IA64::AR_PFS, diff --git a/lib/Target/IA64/IA64InstrInfo.cpp b/lib/Target/IA64/IA64InstrInfo.cpp index 5f53d7d..2a1411a 100644 --- a/lib/Target/IA64/IA64InstrInfo.cpp +++ b/lib/Target/IA64/IA64InstrInfo.cpp @@ -113,7 +113,7 @@ void IA64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, .addFrameIndex(FrameIdx) .addReg(IA64::r2); } else - LLVM_UNREACHABLE("sorry, I don't know how to store this sort of reg" + llvm_unreachable("sorry, I don't know how to store this sort of reg" "in the stack"); } @@ -130,7 +130,7 @@ void IA64InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, } else if (RC == IA64::PRRegisterClass) { Opc = IA64::ST1; } else { - LLVM_UNREACHABLE("sorry, I don't know how to store this sort of reg"); + llvm_unreachable("sorry, I don't know how to store this sort of reg"); } DebugLoc DL = DebugLoc::getUnknownLoc(); @@ -164,7 +164,7 @@ void IA64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, .addReg(IA64::r2) .addReg(IA64::r0); } else { - LLVM_UNREACHABLE("sorry, I don't know how to load this sort of reg" + llvm_unreachable("sorry, I don't know how to load this sort of reg" "from the stack"); } } @@ -181,7 +181,7 @@ void IA64InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, } else if (RC == IA64::PRRegisterClass) { Opc = IA64::LD1; } else { - LLVM_UNREACHABLE("sorry, I don't know how to load this sort of reg"); + llvm_unreachable("sorry, I don't know how to load this sort of reg"); } DebugLoc DL = DebugLoc::getUnknownLoc(); diff --git a/lib/Target/IA64/IA64RegisterInfo.cpp b/lib/Target/IA64/IA64RegisterInfo.cpp index a1a7574..6e3471d 100644 --- a/lib/Target/IA64/IA64RegisterInfo.cpp +++ b/lib/Target/IA64/IA64RegisterInfo.cpp @@ -293,7 +293,7 @@ void IA64RegisterInfo::emitEpilogue(MachineFunction &MF, } unsigned IA64RegisterInfo::getRARegister() const { - LLVM_UNREACHABLE("What is the return address register"); + llvm_unreachable("What is the return address register"); return 0; } @@ -302,17 +302,17 @@ unsigned IA64RegisterInfo::getFrameRegister(MachineFunction &MF) const { } unsigned IA64RegisterInfo::getEHExceptionRegister() const { - LLVM_UNREACHABLE("What is the exception register"); + llvm_unreachable("What is the exception register"); return 0; } unsigned IA64RegisterInfo::getEHHandlerRegister() const { - LLVM_UNREACHABLE("What is the exception handler register"); + llvm_unreachable("What is the exception handler register"); return 0; } int IA64RegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { - LLVM_UNREACHABLE("What is the dwarf register number"); + llvm_unreachable("What is the dwarf register number"); return -1; } diff --git a/lib/Target/MSIL/MSILWriter.cpp b/lib/Target/MSIL/MSILWriter.cpp index 0fdbbf1..591c371 100644 --- a/lib/Target/MSIL/MSILWriter.cpp +++ b/lib/Target/MSIL/MSILWriter.cpp @@ -292,7 +292,7 @@ std::string MSILWriter::getConvModopt(unsigned CallingConvID) { return "modopt([mscorlib]System.Runtime.CompilerServices.CallConvStdcall) "; default: cerr << "CallingConvID = " << CallingConvID << '\n'; - LLVM_UNREACHABLE("Unsupported calling convention"); + llvm_unreachable("Unsupported calling convention"); } return ""; // Not reached } @@ -338,7 +338,7 @@ std::string MSILWriter::getPrimitiveTypeName(const Type* Ty, bool isSigned) { return "float64 "; default: cerr << "Type = " << *Ty << '\n'; - LLVM_UNREACHABLE("Invalid primitive type"); + llvm_unreachable("Invalid primitive type"); } return ""; // Not reached } @@ -366,7 +366,7 @@ std::string MSILWriter::getTypeName(const Type* Ty, bool isSigned, return "valuetype '"+getArrayTypeName(Ty->getTypeID(),Ty)+"' "; default: cerr << "Type = " << *Ty << '\n'; - LLVM_UNREACHABLE("Invalid type in getTypeName()"); + llvm_unreachable("Invalid type in getTypeName()"); } return ""; // Not reached } @@ -410,7 +410,7 @@ std::string MSILWriter::getTypePostfix(const Type* Ty, bool Expand, return "i"+utostr(TD->getTypeAllocSize(Ty)); default: cerr << "TypeID = " << Ty->getTypeID() << '\n'; - LLVM_UNREACHABLE("Invalid type in TypeToPostfix()"); + llvm_unreachable("Invalid type in TypeToPostfix()"); } return ""; // Not reached } @@ -425,7 +425,7 @@ void MSILWriter::printConvToPtr() { printSimpleInstruction("conv.u8"); break; default: - LLVM_UNREACHABLE("Module use not supporting pointer size"); + llvm_unreachable("Module use not supporting pointer size"); } } @@ -437,14 +437,14 @@ void MSILWriter::printPtrLoad(uint64_t N) { // FIXME: Need overflow test? if (!isUInt32(N)) { cerr << "Value = " << utostr(N) << '\n'; - LLVM_UNREACHABLE("32-bit pointer overflowed"); + llvm_unreachable("32-bit pointer overflowed"); } break; case Module::Pointer64: printSimpleInstruction("ldc.i8",utostr(N).c_str()); break; default: - LLVM_UNREACHABLE("Module use not supporting pointer size"); + llvm_unreachable("Module use not supporting pointer size"); } } @@ -480,7 +480,7 @@ void MSILWriter::printConstLoad(const Constant* C) { printPtrLoad(0); } else { cerr << "Constant = " << *C << '\n'; - LLVM_UNREACHABLE("Invalid constant value"); + llvm_unreachable("Invalid constant value"); } Out << '\n'; } @@ -529,7 +529,7 @@ void MSILWriter::printValueLoad(const Value* V) { break; default: cerr << "Value = " << *V << '\n'; - LLVM_UNREACHABLE("Invalid value location"); + llvm_unreachable("Invalid value location"); } } @@ -544,7 +544,7 @@ void MSILWriter::printValueSave(const Value* V) { break; default: cerr << "Value = " << *V << '\n'; - LLVM_UNREACHABLE("Invalid value location"); + llvm_unreachable("Invalid value location"); } } @@ -705,7 +705,7 @@ void MSILWriter::printCastInstruction(unsigned int Op, const Value* V, break; default: cerr << "Opcode = " << Op << '\n'; - LLVM_UNREACHABLE("Invalid conversion instruction"); + llvm_unreachable("Invalid conversion instruction"); } } @@ -796,7 +796,7 @@ void MSILWriter::printFunctionCall(const Value* FnVal, Name = getConvModopt(Invoke->getCallingConv()); else { cerr << "Instruction = " << Inst->getName() << '\n'; - LLVM_UNREACHABLE("Need \"Invoke\" or \"Call\" instruction only"); + llvm_unreachable("Need \"Invoke\" or \"Call\" instruction only"); } if (const Function* F = dyn_cast<Function>(FnVal)) { // Direct call. @@ -844,7 +844,7 @@ void MSILWriter::printIntrinsicCall(const IntrinsicInst* Inst) { break; default: cerr << "Intrinsic ID = " << Inst->getIntrinsicID() << '\n'; - LLVM_UNREACHABLE("Invalid intrinsic function"); + llvm_unreachable("Invalid intrinsic function"); } } @@ -908,7 +908,7 @@ void MSILWriter::printICmpInstruction(unsigned Predicate, const Value* Left, break; default: cerr << "Predicate = " << Predicate << '\n'; - LLVM_UNREACHABLE("Invalid icmp predicate"); + llvm_unreachable("Invalid icmp predicate"); } } @@ -1002,7 +1002,7 @@ void MSILWriter::printFCmpInstruction(unsigned Predicate, const Value* Left, printSimpleInstruction("or"); break; default: - LLVM_UNREACHABLE("Illegal FCmp predicate"); + llvm_unreachable("Illegal FCmp predicate"); } } @@ -1199,10 +1199,10 @@ void MSILWriter::printInstruction(const Instruction* Inst) { printAllocaInstruction(cast<AllocaInst>(Inst)); break; case Instruction::Malloc: - LLVM_UNREACHABLE("LowerAllocationsPass used"); + llvm_unreachable("LowerAllocationsPass used"); break; case Instruction::Free: - LLVM_UNREACHABLE("LowerAllocationsPass used"); + llvm_unreachable("LowerAllocationsPass used"); break; case Instruction::Unreachable: printSimpleInstruction("ldstr", "\"Unreachable instruction\""); @@ -1215,7 +1215,7 @@ void MSILWriter::printInstruction(const Instruction* Inst) { break; default: cerr << "Instruction = " << Inst->getName() << '\n'; - LLVM_UNREACHABLE("Unsupported instruction"); + llvm_unreachable("Unsupported instruction"); } } @@ -1403,7 +1403,7 @@ void MSILWriter::printConstantExpr(const ConstantExpr* CE) { break; default: cerr << "Expression = " << *CE << "\n"; - LLVM_UNREACHABLE("Invalid constant expression"); + llvm_unreachable("Invalid constant expression"); } } @@ -1437,7 +1437,7 @@ void MSILWriter::printStaticInitializerList() { printSimpleInstruction(postfix.c_str()); } else { cerr << "Constant = " << *I->constant << '\n'; - LLVM_UNREACHABLE("Invalid static initializer"); + llvm_unreachable("Invalid static initializer"); } } } @@ -1501,7 +1501,7 @@ unsigned int MSILWriter::getBitWidth(const Type* Ty) { return N; default: cerr << "Bits = " << N << '\n'; - LLVM_UNREACHABLE("Unsupported integer width"); + llvm_unreachable("Unsupported integer width"); } return 0; // Not reached } @@ -1558,12 +1558,12 @@ void MSILWriter::printStaticConstant(const Constant* C, uint64_t& Offset) { // Null pointer initialization if (TySize==4) Out << "int32 (0)"; else if (TySize==8) Out << "int64 (0)"; - else LLVM_UNREACHABLE("Invalid pointer size"); + else llvm_unreachable("Invalid pointer size"); } break; default: cerr << "TypeID = " << Ty->getTypeID() << '\n'; - LLVM_UNREACHABLE("Invalid type in printStaticConstant()"); + llvm_unreachable("Invalid type in printStaticConstant()"); } // Increase offset. Offset += TySize; @@ -1586,7 +1586,7 @@ void MSILWriter::printStaticInitializer(const Constant* C, break; default: cerr << "Type = " << *C << "\n"; - LLVM_UNREACHABLE("Invalid constant type"); + llvm_unreachable("Invalid constant type"); } // Print initializer std::string label = Name; diff --git a/lib/Target/MSP430/MSP430AsmPrinter.cpp b/lib/Target/MSP430/MSP430AsmPrinter.cpp index 0f711ab..b6eb6fe 100644 --- a/lib/Target/MSP430/MSP430AsmPrinter.cpp +++ b/lib/Target/MSP430/MSP430AsmPrinter.cpp @@ -100,7 +100,7 @@ void MSP430AsmPrinter::emitFunctionHeader(const MachineFunction &MF) { EmitAlignment(FnAlign, F); switch (F->getLinkage()) { - default: LLVM_UNREACHABLE("Unknown linkage type!"); + default: llvm_unreachable("Unknown linkage type!"); case Function::InternalLinkage: // Symbols default to internal. case Function::PrivateLinkage: break; @@ -162,7 +162,7 @@ void MSP430AsmPrinter::printMachineInstruction(const MachineInstr *MI) { if (printInstruction(MI)) return; - LLVM_UNREACHABLE("Should not happen"); + llvm_unreachable("Should not happen"); } void MSP430AsmPrinter::printOperand(const MachineInstr *MI, int OpNum, @@ -207,7 +207,7 @@ void MSP430AsmPrinter::printOperand(const MachineInstr *MI, int OpNum, return; } default: - LLVM_UNREACHABLE("Not implemented yet!"); + llvm_unreachable("Not implemented yet!"); } } @@ -231,7 +231,7 @@ void MSP430AsmPrinter::printSrcMemOperand(const MachineInstr *MI, int OpNum, printOperand(MI, OpNum); } } else - LLVM_UNREACHABLE("Unsupported memory operand"); + llvm_unreachable("Unsupported memory operand"); } void MSP430AsmPrinter::printCCOperand(const MachineInstr *MI, int OpNum) { @@ -239,7 +239,7 @@ void MSP430AsmPrinter::printCCOperand(const MachineInstr *MI, int OpNum) { switch (CC) { default: - LLVM_UNREACHABLE("Unsupported CC code"); + llvm_unreachable("Unsupported CC code"); break; case MSP430::COND_E: O << "eq"; diff --git a/lib/Target/MSP430/MSP430ISelLowering.cpp b/lib/Target/MSP430/MSP430ISelLowering.cpp index 69d9cae..219f437 100644 --- a/lib/Target/MSP430/MSP430ISelLowering.cpp +++ b/lib/Target/MSP430/MSP430ISelLowering.cpp @@ -123,7 +123,7 @@ SDValue MSP430TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG); default: - LLVM_UNREACHABLE("unimplemented operand"); + llvm_unreachable("unimplemented operand"); return SDValue(); } } @@ -144,7 +144,7 @@ SDValue MSP430TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); switch (CC) { default: - LLVM_UNREACHABLE("Unsupported calling convention"); + llvm_unreachable("Unsupported calling convention"); case CallingConv::C: case CallingConv::Fast: return LowerCCCArguments(Op, DAG); @@ -156,7 +156,7 @@ SDValue MSP430TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) { unsigned CallingConv = TheCall->getCallingConv(); switch (CallingConv) { default: - LLVM_UNREACHABLE("Unsupported calling convention"); + llvm_unreachable("Unsupported calling convention"); case CallingConv::Fast: case CallingConv::C: return LowerCCCCallTo(Op, DAG, CallingConv); @@ -197,7 +197,7 @@ SDValue MSP430TargetLowering::LowerCCCArguments(SDValue Op, cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: " << RegVT.getSimpleVT() << "\n"; #endif - llvm_unreachable(); + llvm_unreachable(0); } case MVT::i16: unsigned VReg = @@ -331,7 +331,7 @@ SDValue MSP430TargetLowering::LowerCCCCallTo(SDValue Op, SelectionDAG &DAG, // Promote the value if needed. switch (VA.getLocInfo()) { - default: LLVM_UNREACHABLE("Unknown loc info!"); + default: llvm_unreachable("Unknown loc info!"); case CCValAssign::Full: break; case CCValAssign::SExt: Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); @@ -516,7 +516,7 @@ static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, unsigned &TargetCC, // FIXME: Handle jump negative someday TargetCC = MSP430::COND_INVALID; switch (CC) { - default: LLVM_UNREACHABLE("Invalid integer condition!"); + default: llvm_unreachable("Invalid integer condition!"); case ISD::SETEQ: TargetCC = MSP430::COND_E; // aka COND_Z break; diff --git a/lib/Target/MSP430/MSP430InstrInfo.cpp b/lib/Target/MSP430/MSP430InstrInfo.cpp index 8dc71df..37fbb6d 100644 --- a/lib/Target/MSP430/MSP430InstrInfo.cpp +++ b/lib/Target/MSP430/MSP430InstrInfo.cpp @@ -45,7 +45,7 @@ void MSP430InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, .addFrameIndex(FrameIdx).addImm(0) .addReg(SrcReg, getKillRegState(isKill)); else - LLVM_UNREACHABLE("Cannot store this register to stack slot!"); + llvm_unreachable("Cannot store this register to stack slot!"); } void MSP430InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, @@ -62,7 +62,7 @@ void MSP430InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, BuildMI(MBB, MI, DL, get(MSP430::MOV8rm)) .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0); else - LLVM_UNREACHABLE("Cannot store this register to stack slot!"); + llvm_unreachable("Cannot store this register to stack slot!"); } bool MSP430InstrInfo::copyRegToReg(MachineBasicBlock &MBB, @@ -172,7 +172,7 @@ MSP430InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, // Conditional branch. unsigned Count = 0; - LLVM_UNREACHABLE("Implement conditional branches!"); + llvm_unreachable("Implement conditional branches!"); return Count; } diff --git a/lib/Target/MSP430/MSP430RegisterInfo.cpp b/lib/Target/MSP430/MSP430RegisterInfo.cpp index 2c96f85..6b2b555 100644 --- a/lib/Target/MSP430/MSP430RegisterInfo.cpp +++ b/lib/Target/MSP430/MSP430RegisterInfo.cpp @@ -292,7 +292,7 @@ void MSP430RegisterInfo::emitEpilogue(MachineFunction &MF, switch (RetOpcode) { case MSP430::RET: break; // These are ok default: - LLVM_UNREACHABLE("Can only insert epilog into returning blocks"); + llvm_unreachable("Can only insert epilog into returning blocks"); } // Get the number of bytes to allocate from the FrameInfo @@ -328,7 +328,7 @@ void MSP430RegisterInfo::emitEpilogue(MachineFunction &MF, // mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes); if (MFI->hasVarSizedObjects()) { - LLVM_UNREACHABLE("Not implemented yet!"); + llvm_unreachable("Not implemented yet!"); } else { // adjust stack pointer back: SPW += numbytes if (NumBytes) { @@ -350,7 +350,7 @@ unsigned MSP430RegisterInfo::getFrameRegister(MachineFunction &MF) const { } int MSP430RegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { - LLVM_UNREACHABLE("Not implemented yet!"); + llvm_unreachable("Not implemented yet!"); return 0; } diff --git a/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp b/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp index 9768710..7a0e5e8 100644 --- a/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp +++ b/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp @@ -216,7 +216,7 @@ emitCurrentABIString(void) default: break; } - LLVM_UNREACHABLE("Unknown Mips ABI"); + llvm_unreachable("Unknown Mips ABI"); return NULL; } @@ -406,7 +406,7 @@ printOperand(const MachineInstr *MI, int opNum) break; default: - LLVM_UNREACHABLE("<unknown operand type>"); + llvm_unreachable("<unknown operand type>"); } if (closeP) O << ")"; @@ -545,13 +545,13 @@ printModuleLevelGV(const GlobalVariable* GVar) { printSizeAndType = false; break; case GlobalValue::GhostLinkage: - LLVM_UNREACHABLE("Should not have any unmaterialized functions!"); + llvm_unreachable("Should not have any unmaterialized functions!"); case GlobalValue::DLLImportLinkage: - LLVM_UNREACHABLE("DLLImport linkage is not supported by this target!"); + llvm_unreachable("DLLImport linkage is not supported by this target!"); case GlobalValue::DLLExportLinkage: - LLVM_UNREACHABLE("DLLExport linkage is not supported by this target!"); + llvm_unreachable("DLLExport linkage is not supported by this target!"); default: - LLVM_UNREACHABLE("Unknown linkage type!"); + llvm_unreachable("Unknown linkage type!"); } EmitAlignment(Align, GVar); diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index f3fa179..0b10c9a 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -248,7 +248,7 @@ static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) { static unsigned FPBranchCodeToOpc(Mips::FPBranchCode BC) { switch(BC) { default: - LLVM_UNREACHABLE("Unknown branch code"); + llvm_unreachable("Unknown branch code"); case Mips::BRANCH_T : return Mips::BC1T; case Mips::BRANCH_F : return Mips::BC1F; case Mips::BRANCH_TL : return Mips::BC1TL; @@ -258,7 +258,7 @@ static unsigned FPBranchCodeToOpc(Mips::FPBranchCode BC) { static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) { switch (CC) { - default: LLVM_UNREACHABLE("Unknown fp condition code!"); + default: llvm_unreachable("Unknown fp condition code!"); case ISD::SETEQ: case ISD::SETOEQ: return Mips::FCOND_EQ; case ISD::SETUNE: return Mips::FCOND_OGL; @@ -542,14 +542,14 @@ LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo); } - LLVM_UNREACHABLE("Dont know how to handle GlobalAddress"); + llvm_unreachable("Dont know how to handle GlobalAddress"); return SDValue(0,0); } SDValue MipsTargetLowering:: LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) { - LLVM_UNREACHABLE("TLS not implemented for MIPS."); + llvm_unreachable("TLS not implemented for MIPS."); return SDValue(); // Not reached } @@ -753,7 +753,7 @@ LowerCALL(SDValue Op, SelectionDAG &DAG) // Promote the value if needed. switch (VA.getLocInfo()) { - default: LLVM_UNREACHABLE("Unknown loc info!"); + default: llvm_unreachable("Unknown loc info!"); case CCValAssign::Full: if (Subtarget->isABI_O32() && VA.isRegLoc()) { if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32) @@ -978,7 +978,7 @@ LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) if (!Subtarget->isSingleFloat()) RC = Mips::AFGR64RegisterClass; } else - LLVM_UNREACHABLE("RegVT not supported by FORMAL_ARGUMENTS Lowering"); + llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering"); // Transform the arguments stored on // physical registers into virtual ones @@ -1140,7 +1140,7 @@ LowerRET(SDValue Op, SelectionDAG &DAG) unsigned Reg = MipsFI->getSRetReturnReg(); if (!Reg) - LLVM_UNREACHABLE("sret virtual register not created in the entry block"); + llvm_unreachable("sret virtual register not created in the entry block"); SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag); diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp index 1150765..34b5a6e 100644 --- a/lib/Target/Mips/MipsInstrInfo.cpp +++ b/lib/Target/Mips/MipsInstrInfo.cpp @@ -373,7 +373,7 @@ static Mips::CondCode GetCondFromBranchOpc(unsigned BrOpc) unsigned Mips::GetCondBranchFromCond(Mips::CondCode CC) { switch (CC) { - default: LLVM_UNREACHABLE("Illegal condition code!"); + default: llvm_unreachable("Illegal condition code!"); case Mips::COND_E : return Mips::BEQ; case Mips::COND_NE : return Mips::BNE; case Mips::COND_GZ : return Mips::BGTZ; @@ -422,7 +422,7 @@ unsigned Mips::GetCondBranchFromCond(Mips::CondCode CC) Mips::CondCode Mips::GetOppositeBranchCondition(Mips::CondCode CC) { switch (CC) { - default: LLVM_UNREACHABLE("Illegal condition code!"); + default: llvm_unreachable("Illegal condition code!"); case Mips::COND_E : return Mips::COND_NE; case Mips::COND_NE : return Mips::COND_E; case Mips::COND_GZ : return Mips::COND_LEZ; diff --git a/lib/Target/Mips/MipsInstrInfo.h b/lib/Target/Mips/MipsInstrInfo.h index 9c47d8e..1fb678f 100644 --- a/lib/Target/Mips/MipsInstrInfo.h +++ b/lib/Target/Mips/MipsInstrInfo.h @@ -93,7 +93,7 @@ namespace Mips { inline static const char *MipsFCCToString(Mips::CondCode CC) { switch (CC) { - default: LLVM_UNREACHABLE("Unknown condition code"); + default: llvm_unreachable("Unknown condition code"); case FCOND_F: case FCOND_T: return "f"; case FCOND_UN: diff --git a/lib/Target/Mips/MipsRegisterInfo.cpp b/lib/Target/Mips/MipsRegisterInfo.cpp index 816d7c7..c7aea69 100644 --- a/lib/Target/Mips/MipsRegisterInfo.cpp +++ b/lib/Target/Mips/MipsRegisterInfo.cpp @@ -80,7 +80,7 @@ getRegisterNumbering(unsigned RegEnum) case Mips::SP : case Mips::F29: return 29; case Mips::FP : case Mips::F30: case Mips::D15: return 30; case Mips::RA : case Mips::F31: return 31; - default: LLVM_UNREACHABLE("Unknown register number!"); + default: llvm_unreachable("Unknown register number!"); } return 0; // Not reached } @@ -516,19 +516,19 @@ getFrameRegister(MachineFunction &MF) const { unsigned MipsRegisterInfo:: getEHExceptionRegister() const { - LLVM_UNREACHABLE("What is the exception register"); + llvm_unreachable("What is the exception register"); return 0; } unsigned MipsRegisterInfo:: getEHHandlerRegister() const { - LLVM_UNREACHABLE("What is the exception handler register"); + llvm_unreachable("What is the exception handler register"); return 0; } int MipsRegisterInfo:: getDwarfRegNum(unsigned RegNum, bool isEH) const { - LLVM_UNREACHABLE("What is the dwarf register number"); + llvm_unreachable("What is the dwarf register number"); return -1; } diff --git a/lib/Target/PIC16/PIC16.h b/lib/Target/PIC16/PIC16.h index 6af4664..3b6fcee 100644 --- a/lib/Target/PIC16/PIC16.h +++ b/lib/Target/PIC16/PIC16.h @@ -308,7 +308,7 @@ namespace PIC16CC { inline static const char *PIC16CondCodeToString(PIC16CC::CondCodes CC) { switch (CC) { - default: LLVM_UNREACHABLE("Unknown condition code"); + default: llvm_unreachable("Unknown condition code"); case PIC16CC::NE: return "ne"; case PIC16CC::EQ: return "eq"; case PIC16CC::LT: return "lt"; @@ -324,7 +324,7 @@ namespace PIC16CC { inline static bool isSignedComparison(PIC16CC::CondCodes CC) { switch (CC) { - default: LLVM_UNREACHABLE("Unknown condition code"); + default: llvm_unreachable("Unknown condition code"); case PIC16CC::NE: case PIC16CC::EQ: case PIC16CC::LT: diff --git a/lib/Target/PIC16/PIC16AsmPrinter.cpp b/lib/Target/PIC16/PIC16AsmPrinter.cpp index d80476c..b6401df 100644 --- a/lib/Target/PIC16/PIC16AsmPrinter.cpp +++ b/lib/Target/PIC16/PIC16AsmPrinter.cpp @@ -128,7 +128,7 @@ void PIC16AsmPrinter::printOperand(const MachineInstr *MI, int opNum) { if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) O << TM.getRegisterInfo()->get(MO.getReg()).AsmName; else - LLVM_UNREACHABLE("not implemented"); + llvm_unreachable("not implemented"); return; case MachineOperand::MO_Immediate: @@ -155,7 +155,7 @@ void PIC16AsmPrinter::printOperand(const MachineInstr *MI, int opNum) { return; default: - LLVM_UNREACHABLE(" Operand type not supported."); + llvm_unreachable(" Operand type not supported."); } } diff --git a/lib/Target/PIC16/PIC16ISelLowering.cpp b/lib/Target/PIC16/PIC16ISelLowering.cpp index c8c353f..9a3d704 100644 --- a/lib/Target/PIC16/PIC16ISelLowering.cpp +++ b/lib/Target/PIC16/PIC16ISelLowering.cpp @@ -1228,7 +1228,7 @@ SDValue PIC16TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) { // return should have odd number of operands if ((Op.getNumOperands() % 2) == 0 ) { - LLVM_UNREACHABLE("Do not know how to return this many arguments!"); + llvm_unreachable("Do not know how to return this many arguments!"); } // Number of values to return @@ -1697,7 +1697,7 @@ SDValue PIC16TargetLowering::PerformDAGCombine(SDNode *N, static PIC16CC::CondCodes IntCCToPIC16CC(ISD::CondCode CC) { switch (CC) { - default: LLVM_UNREACHABLE("Unknown condition code!"); + default: llvm_unreachable("Unknown condition code!"); case ISD::SETNE: return PIC16CC::NE; case ISD::SETEQ: return PIC16CC::EQ; case ISD::SETGT: return PIC16CC::GT; diff --git a/lib/Target/PIC16/PIC16InstrInfo.cpp b/lib/Target/PIC16/PIC16InstrInfo.cpp index dad0266..cb0c41b 100644 --- a/lib/Target/PIC16/PIC16InstrInfo.cpp +++ b/lib/Target/PIC16/PIC16InstrInfo.cpp @@ -105,7 +105,7 @@ void PIC16InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, .addImm(1); // Emit banksel for it. } else - LLVM_UNREACHABLE("Can't store this register to stack slot"); + llvm_unreachable("Can't store this register to stack slot"); } void PIC16InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, @@ -145,7 +145,7 @@ void PIC16InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, .addImm(1); // Emit banksel for it. } else - LLVM_UNREACHABLE("Can't load this register from stack slot"); + llvm_unreachable("Can't load this register from stack slot"); } bool PIC16InstrInfo::copyRegToReg (MachineBasicBlock &MBB, diff --git a/lib/Target/PIC16/PIC16RegisterInfo.cpp b/lib/Target/PIC16/PIC16RegisterInfo.cpp index bb4f278..bbdb353 100644 --- a/lib/Target/PIC16/PIC16RegisterInfo.cpp +++ b/lib/Target/PIC16/PIC16RegisterInfo.cpp @@ -65,17 +65,17 @@ emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const int PIC16RegisterInfo:: getDwarfRegNum(unsigned RegNum, bool isEH) const { - LLVM_UNREACHABLE("Not keeping track of debug information yet!!"); + llvm_unreachable("Not keeping track of debug information yet!!"); return -1; } unsigned PIC16RegisterInfo::getFrameRegister(MachineFunction &MF) const { - LLVM_UNREACHABLE("PIC16 Does not have any frame register"); + llvm_unreachable("PIC16 Does not have any frame register"); return 0; } unsigned PIC16RegisterInfo::getRARegister() const { - LLVM_UNREACHABLE("PIC16 Does not have any return address register"); + llvm_unreachable("PIC16 Does not have any return address register"); return 0; } diff --git a/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp b/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp index cec3273..fddc1c2 100644 --- a/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp +++ b/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp @@ -71,7 +71,7 @@ namespace { unsigned enumRegToMachineReg(unsigned enumReg) { switch (enumReg) { - default: LLVM_UNREACHABLE("Unhandled register!"); + default: llvm_unreachable("Unhandled register!"); case PPC::CR0: return 0; case PPC::CR1: return 1; case PPC::CR2: return 2; @@ -81,7 +81,7 @@ namespace { case PPC::CR6: return 6; case PPC::CR7: return 7; } - llvm_unreachable(); + llvm_unreachable(0); } /// printInstruction - This method is automatically generated by tablegen @@ -349,7 +349,7 @@ namespace { void PPCAsmPrinter::printOp(const MachineOperand &MO) { switch (MO.getType()) { case MachineOperand::MO_Immediate: - LLVM_UNREACHABLE("printOp() does not handle immediate values"); + llvm_unreachable("printOp() does not handle immediate values"); case MachineOperand::MO_MachineBasicBlock: printBasicBlockLabel(MO.getMBB()); @@ -551,7 +551,7 @@ void PPCAsmPrinter::printMachineInstruction(const MachineInstr *MI) { if (printInstruction(MI)) return; // Printer was automatically generated - LLVM_UNREACHABLE("Unhandled instruction in asm writer!"); + llvm_unreachable("Unhandled instruction in asm writer!"); } /// runOnMachineFunction - This uses the printMachineInstruction() @@ -571,7 +571,7 @@ bool PPCLinuxAsmPrinter::runOnMachineFunction(MachineFunction &MF) { SwitchToSection(TAI->SectionForGlobal(F)); switch (F->getLinkage()) { - default: LLVM_UNREACHABLE("Unknown linkage type!"); + default: llvm_unreachable("Unknown linkage type!"); case Function::PrivateLinkage: case Function::InternalLinkage: // Symbols default to internal. break; @@ -706,7 +706,7 @@ void PPCLinuxAsmPrinter::printModuleLevelGV(const GlobalVariable* GVar) { case GlobalValue::PrivateLinkage: break; default: - LLVM_UNREACHABLE("Unknown linkage type!"); + llvm_unreachable("Unknown linkage type!"); } EmitAlignment(Align, GVar); @@ -748,7 +748,7 @@ bool PPCDarwinAsmPrinter::runOnMachineFunction(MachineFunction &MF) { SwitchToSection(TAI->SectionForGlobal(F)); switch (F->getLinkage()) { - default: LLVM_UNREACHABLE("Unknown linkage type!"); + default: llvm_unreachable("Unknown linkage type!"); case Function::PrivateLinkage: case Function::InternalLinkage: // Symbols default to internal. break; @@ -936,7 +936,7 @@ void PPCDarwinAsmPrinter::printModuleLevelGV(const GlobalVariable* GVar) { case GlobalValue::PrivateLinkage: break; default: - LLVM_UNREACHABLE("Unknown linkage type!"); + llvm_unreachable("Unknown linkage type!"); } EmitAlignment(Align, GVar); diff --git a/lib/Target/PowerPC/PPCCodeEmitter.cpp b/lib/Target/PowerPC/PPCCodeEmitter.cpp index 4943e5c..4090a22 100644 --- a/lib/Target/PowerPC/PPCCodeEmitter.cpp +++ b/lib/Target/PowerPC/PPCCodeEmitter.cpp @@ -181,7 +181,7 @@ unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI, assert(MovePCtoLROffset && "MovePCtoLR not seen yet?"); } switch (MI.getOpcode()) { - default: MI.dump(); LLVM_UNREACHABLE("Unknown instruction for relocation!"); + default: MI.dump(); llvm_unreachable("Unknown instruction for relocation!"); case PPC::LIS: case PPC::LIS8: case PPC::ADDIS: @@ -268,7 +268,7 @@ unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI, #ifndef NDEBUG cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n"; #endif - llvm_unreachable(); + llvm_unreachable(0); } return rv; diff --git a/lib/Target/PowerPC/PPCHazardRecognizers.cpp b/lib/Target/PowerPC/PPCHazardRecognizers.cpp index 244d395..e754d9d 100644 --- a/lib/Target/PowerPC/PPCHazardRecognizers.cpp +++ b/lib/Target/PowerPC/PPCHazardRecognizers.cpp @@ -142,7 +142,7 @@ getHazardType(SUnit *SU) { return Hazard; switch (InstrType) { - default: LLVM_UNREACHABLE("Unknown instruction type!"); + default: llvm_unreachable("Unknown instruction type!"); case PPCII::PPC970_FXU: case PPCII::PPC970_LSU: case PPCII::PPC970_FPU: @@ -168,7 +168,7 @@ getHazardType(SUnit *SU) { if (isLoad && NumStores) { unsigned LoadSize; switch (Opcode) { - default: LLVM_UNREACHABLE("Unknown load!"); + default: llvm_unreachable("Unknown load!"); case PPC::LBZ: case PPC::LBZU: case PPC::LBZX: case PPC::LBZ8: case PPC::LBZU8: @@ -236,7 +236,7 @@ void PPCHazardRecognizer970::EmitInstruction(SUnit *SU) { if (isStore) { unsigned ThisStoreSize; switch (Opcode) { - default: LLVM_UNREACHABLE("Unknown store instruction!"); + default: llvm_unreachable("Unknown store instruction!"); case PPC::STB: case PPC::STB8: case PPC::STBU: case PPC::STBU8: case PPC::STBX: case PPC::STBX8: diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index b17e54d..9221355 100644 --- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -602,8 +602,8 @@ static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) { case ISD::SETONE: case ISD::SETOLE: case ISD::SETOGE: - LLVM_UNREACHABLE("Should be lowered by legalize!"); - default: LLVM_UNREACHABLE("Unknown condition!"); + llvm_unreachable("Should be lowered by legalize!"); + default: llvm_unreachable("Unknown condition!"); case ISD::SETOEQ: case ISD::SETEQ: return PPC::PRED_EQ; case ISD::SETUNE: @@ -634,7 +634,7 @@ static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert, int &Other) { Invert = false; Other = -1; switch (CC) { - default: LLVM_UNREACHABLE("Unknown condition!"); + default: llvm_unreachable("Unknown condition!"); case ISD::SETOLT: case ISD::SETLT: return 0; // Bit #0 = SETOLT case ISD::SETOGT: @@ -653,7 +653,7 @@ static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert, int &Other) { case ISD::SETOGE: case ISD::SETOLE: case ISD::SETONE: - LLVM_UNREACHABLE("Invalid branch code: should be expanded by legalize"); + llvm_unreachable("Invalid branch code: should be expanded by legalize"); // These are invalid for floating point. Assume integer. case ISD::SETULT: return 0; case ISD::SETUGT: return 1; @@ -941,7 +941,7 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) { // Handle PPC32 integer and normal FP loads. assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); switch (LoadedVT.getSimpleVT()) { - default: LLVM_UNREACHABLE("Invalid PPC load type!"); + default: llvm_unreachable("Invalid PPC load type!"); case MVT::f64: Opcode = PPC::LFDU; break; case MVT::f32: Opcode = PPC::LFSU; break; case MVT::i32: Opcode = PPC::LWZU; break; @@ -953,7 +953,7 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) { assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!"); assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); switch (LoadedVT.getSimpleVT()) { - default: LLVM_UNREACHABLE("Invalid PPC load type!"); + default: llvm_unreachable("Invalid PPC load type!"); case MVT::i64: Opcode = PPC::LDU; break; case MVT::i32: Opcode = PPC::LWZU8; break; case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break; @@ -970,7 +970,7 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) { PPCLowering.getPointerTy(), MVT::Other, Ops, 3); } else { - LLVM_UNREACHABLE("R+R preindex loads not supported yet!"); + llvm_unreachable("R+R preindex loads not supported yet!"); } } diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 842361f..5cabf04 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -1156,7 +1156,7 @@ SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) { SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) { - LLVM_UNREACHABLE("TLS not implemented for PPC."); + llvm_unreachable("TLS not implemented for PPC."); return SDValue(); // Not reached } @@ -1251,7 +1251,7 @@ SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG, unsigned VarArgsNumFPR, const PPCSubtarget &Subtarget) { - LLVM_UNREACHABLE("VAARG not yet implemented for the SVR4 ABI!"); + llvm_unreachable("VAARG not yet implemented for the SVR4 ABI!"); return SDValue(); // Not reached } @@ -1544,7 +1544,7 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS_SVR4(SDValue Op, switch (ValVT.getSimpleVT()) { default: - LLVM_UNREACHABLE("ValVT not supported by FORMAL_ARGUMENTS Lowering"); + llvm_unreachable("ValVT not supported by FORMAL_ARGUMENTS Lowering"); case MVT::i32: RC = PPC::GPRCRegisterClass; break; @@ -1785,7 +1785,7 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS_Darwin(SDValue Op, } switch(ObjectVT.getSimpleVT()) { - default: LLVM_UNREACHABLE("Unhandled argument type!"); + default: llvm_unreachable("Unhandled argument type!"); case MVT::i32: case MVT::f32: VecArgOffset += isPPC64 ? 8 : 4; @@ -1892,7 +1892,7 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS_Darwin(SDValue Op, } switch (ObjectVT.getSimpleVT()) { - default: LLVM_UNREACHABLE("Unhandled argument type!"); + default: llvm_unreachable("Unhandled argument type!"); case MVT::i32: if (!isPPC64) { if (GPR_idx != Num_GPR_Regs) { @@ -2591,7 +2591,7 @@ SDValue PPCTargetLowering::LowerCALL_SVR4(SDValue Op, SelectionDAG &DAG, cerr << "Call operand #" << i << " has unhandled type " << ArgVT.getMVTString() << "\n"; #endif - llvm_unreachable(); + llvm_unreachable(0); } } } else { @@ -2902,7 +2902,7 @@ SDValue PPCTargetLowering::LowerCALL_Darwin(SDValue Op, SelectionDAG &DAG, } switch (Arg.getValueType().getSimpleVT()) { - default: LLVM_UNREACHABLE("Unexpected ValueType for argument!"); + default: llvm_unreachable("Unexpected ValueType for argument!"); case MVT::i32: case MVT::i64: if (GPR_idx != NumGPRs) { @@ -3309,7 +3309,7 @@ SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, SDValue Tmp; switch (Op.getValueType().getSimpleVT()) { - default: LLVM_UNREACHABLE("Unhandled FP_TO_INT type in custom expander!"); + default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!"); case MVT::i32: Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ : PPCISD::FCTIDZ, @@ -3795,7 +3795,7 @@ static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, int ShufIdxs[16]; switch (OpNum) { - default: LLVM_UNREACHABLE("Unknown i32 permute!"); + default: llvm_unreachable("Unknown i32 permute!"); case OP_VMRGHW: ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3; ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19; @@ -4147,7 +4147,7 @@ SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) { } return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops); } else { - LLVM_UNREACHABLE("Unknown mul to lower!"); + llvm_unreachable("Unknown mul to lower!"); } } @@ -4155,7 +4155,7 @@ SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) { /// SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { switch (Op.getOpcode()) { - default: LLVM_UNREACHABLE("Wasn't expecting to be able to lower this!"); + default: llvm_unreachable("Wasn't expecting to be able to lower this!"); case ISD::ConstantPool: return LowerConstantPool(Op, DAG); case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); @@ -4817,7 +4817,7 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, BB = exitMBB; BuildMI(BB, dl, TII->get(PPC::SRW),dest).addReg(TmpReg).addReg(ShiftReg); } else { - LLVM_UNREACHABLE("Unexpected instr type to insert"); + llvm_unreachable("Unexpected instr type to insert"); } F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. @@ -5192,7 +5192,7 @@ void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, char Letter, if (!CST) return; // Must be an immediate to match. unsigned Value = CST->getZExtValue(); switch (Letter) { - default: LLVM_UNREACHABLE("Unknown constraint letter!"); + default: llvm_unreachable("Unknown constraint letter!"); case 'I': // "I" is a signed 16-bit constant. if ((short)Value == (int)Value) Result = DAG.getTargetConstant(Value, Op.getValueType()); diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp index 63adf32..8b5e4b2 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -487,7 +487,7 @@ PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF, .addReg(PPC::R0) .addReg(PPC::R0)); } else { - LLVM_UNREACHABLE("Unknown regclass!"); + llvm_unreachable("Unknown regclass!"); } return false; @@ -538,7 +538,7 @@ void PPCInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, } else if (RC == PPC::VRRCRegisterClass) { Opc = PPC::STVX; } else { - LLVM_UNREACHABLE("Unknown regclass!"); + llvm_unreachable("Unknown regclass!"); } MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)) .addReg(SrcReg, getKillRegState(isKill)); @@ -634,7 +634,7 @@ PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL, NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0) .addReg(PPC::R0)); } else { - LLVM_UNREACHABLE("Unknown regclass!"); + llvm_unreachable("Unknown regclass!"); } } @@ -676,7 +676,7 @@ void PPCInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, } else if (RC == PPC::VRRCRegisterClass) { Opc = PPC::LVX; } else { - LLVM_UNREACHABLE("Unknown regclass!"); + llvm_unreachable("Unknown regclass!"); } DebugLoc DL = DebugLoc::getUnknownLoc(); MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); diff --git a/lib/Target/PowerPC/PPCJITInfo.cpp b/lib/Target/PowerPC/PPCJITInfo.cpp index 91deca1..ef25d92 100644 --- a/lib/Target/PowerPC/PPCJITInfo.cpp +++ b/lib/Target/PowerPC/PPCJITInfo.cpp @@ -199,7 +199,7 @@ asm( ); #else void PPC32CompilationCallback() { - LLVM_UNREACHABLE("This is not a power pc, you can't execute this!"); + llvm_unreachable("This is not a power pc, you can't execute this!"); } #endif @@ -265,7 +265,7 @@ asm( ); #else void PPC64CompilationCallback() { - LLVM_UNREACHABLE("This is not a power pc, you can't execute this!"); + llvm_unreachable("This is not a power pc, you can't execute this!"); } #endif @@ -383,7 +383,7 @@ void PPCJITInfo::relocate(void *Function, MachineRelocation *MR, unsigned *RelocPos = (unsigned*)Function + MR->getMachineCodeOffset()/4; intptr_t ResultPtr = (intptr_t)MR->getResultPointer(); switch ((PPC::RelocationType)MR->getRelocationType()) { - default: LLVM_UNREACHABLE("Unknown relocation type!"); + default: llvm_unreachable("Unknown relocation type!"); case PPC::reloc_pcrel_bx: // PC-relative relocation for b and bl instructions. ResultPtr = (ResultPtr-(intptr_t)RelocPos) >> 2; diff --git a/lib/Target/PowerPC/PPCMachOWriterInfo.cpp b/lib/Target/PowerPC/PPCMachOWriterInfo.cpp index 9e57bd9..4c14454 100644 --- a/lib/Target/PowerPC/PPCMachOWriterInfo.cpp +++ b/lib/Target/PowerPC/PPCMachOWriterInfo.cpp @@ -47,9 +47,9 @@ unsigned PPCMachOWriterInfo::GetTargetRelocation(MachineRelocation &MR, Addr = (uintptr_t)MR.getResultPointer() + ToAddr; switch ((PPC::RelocationType)MR.getRelocationType()) { - default: LLVM_UNREACHABLE("Unknown PPC relocation type!"); + default: llvm_unreachable("Unknown PPC relocation type!"); case PPC::reloc_absolute_low_ix: - LLVM_UNREACHABLE("Unhandled PPC relocation type!"); + llvm_unreachable("Unhandled PPC relocation type!"); break; case PPC::reloc_vanilla: { diff --git a/lib/Target/PowerPC/PPCPredicates.cpp b/lib/Target/PowerPC/PPCPredicates.cpp index bb9e166..12bb0a1 100644 --- a/lib/Target/PowerPC/PPCPredicates.cpp +++ b/lib/Target/PowerPC/PPCPredicates.cpp @@ -18,7 +18,7 @@ using namespace llvm; PPC::Predicate PPC::InvertPredicate(PPC::Predicate Opcode) { switch (Opcode) { - default: LLVM_UNREACHABLE("Unknown PPC branch opcode!"); + default: llvm_unreachable("Unknown PPC branch opcode!"); case PPC::PRED_EQ: return PPC::PRED_NE; case PPC::PRED_NE: return PPC::PRED_EQ; case PPC::PRED_LT: return PPC::PRED_GE; diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index 6f807fe..6016eb4 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -113,7 +113,7 @@ unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) { case R30: case X30: case F30: case V30: case CR7EQ: return 30; case R31: case X31: case F31: case V31: case CR7UN: return 31; default: - LLVM_UNREACHABLE("Unhandled reg in PPCRegisterInfo::getRegisterNumbering!"); + llvm_unreachable("Unhandled reg in PPCRegisterInfo::getRegisterNumbering!"); } } @@ -1065,7 +1065,7 @@ PPCRegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) MinVR = Reg; } } else { - LLVM_UNREACHABLE("Unknown RegisterClass!"); + llvm_unreachable("Unknown RegisterClass!"); } } diff --git a/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp b/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp index 04e1cc8..e01ce72 100644 --- a/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp +++ b/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp @@ -185,7 +185,7 @@ void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum) { << MO.getIndex(); break; default: - LLVM_UNREACHABLE("<unknown operand type>"); + llvm_unreachable("<unknown operand type>"); } if (CloseParen) O << ")"; } @@ -299,13 +299,13 @@ void SparcAsmPrinter::printModuleLevelGV(const GlobalVariable* GVar) { case GlobalValue::InternalLinkage: break; case GlobalValue::GhostLinkage: - LLVM_UNREACHABLE("Should not have any unmaterialized functions!"); + llvm_unreachable("Should not have any unmaterialized functions!"); case GlobalValue::DLLImportLinkage: - LLVM_UNREACHABLE("DLLImport linkage is not supported by this target!"); + llvm_unreachable("DLLImport linkage is not supported by this target!"); case GlobalValue::DLLExportLinkage: - LLVM_UNREACHABLE("DLLExport linkage is not supported by this target!"); + llvm_unreachable("DLLExport linkage is not supported by this target!"); default: - LLVM_UNREACHABLE("Unknown linkage type!"); + llvm_unreachable("Unknown linkage type!"); } EmitAlignment(Align, GVar); diff --git a/lib/Target/Sparc/FPMover.cpp b/lib/Target/Sparc/FPMover.cpp index 0f251de..8ac459a 100644 --- a/lib/Target/Sparc/FPMover.cpp +++ b/lib/Target/Sparc/FPMover.cpp @@ -76,7 +76,7 @@ static void getDoubleRegPair(unsigned DoubleReg, unsigned &EvenReg, OddReg = OddHalvesOfPairs[i]; return; } - LLVM_UNREACHABLE("Can't find reg"); + llvm_unreachable("Can't find reg"); } /// runOnMachineBasicBlock - Fixup FpMOVD instructions in this MBB. @@ -109,7 +109,7 @@ bool FPMover::runOnMachineBasicBlock(MachineBasicBlock &MBB) { else if (MI->getOpcode() == SP::FpABSD) MI->setDesc(TII->get(SP::FABSS)); else - LLVM_UNREACHABLE("Unknown opcode!"); + llvm_unreachable("Unknown opcode!"); MI->getOperand(0).setReg(EvenDestReg); MI->getOperand(1).setReg(EvenSrcReg); diff --git a/lib/Target/Sparc/Sparc.h b/lib/Target/Sparc/Sparc.h index 539e50a..82bc7e7 100644 --- a/lib/Target/Sparc/Sparc.h +++ b/lib/Target/Sparc/Sparc.h @@ -84,7 +84,7 @@ namespace llvm { inline static const char *SPARCCondCodeToString(SPCC::CondCodes CC) { switch (CC) { - default: LLVM_UNREACHABLE("Unknown condition code"); + default: llvm_unreachable("Unknown condition code"); case SPCC::ICC_NE: return "ne"; case SPCC::ICC_E: return "e"; case SPCC::ICC_G: return "g"; diff --git a/lib/Target/Sparc/SparcISelLowering.cpp b/lib/Target/Sparc/SparcISelLowering.cpp index 4f5060e..3705ecb 100644 --- a/lib/Target/Sparc/SparcISelLowering.cpp +++ b/lib/Target/Sparc/SparcISelLowering.cpp @@ -99,7 +99,7 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG, MVT ObjectVT = getValueType(I->getType()); switch (ObjectVT.getSimpleVT()) { - default: LLVM_UNREACHABLE("Unhandled argument type!"); + default: llvm_unreachable("Unhandled argument type!"); case MVT::i1: case MVT::i8: case MVT::i16: @@ -252,7 +252,7 @@ static SDValue LowerCALL(SDValue Op, SelectionDAG &DAG) { unsigned ArgsSize = 0; for (unsigned i = 0, e = TheCall->getNumArgs(); i != e; ++i) { switch (TheCall->getArg(i).getValueType().getSimpleVT()) { - default: LLVM_UNREACHABLE("Unknown value type!"); + default: llvm_unreachable("Unknown value type!"); case MVT::i1: case MVT::i8: case MVT::i16: @@ -290,7 +290,7 @@ static SDValue LowerCALL(SDValue Op, SelectionDAG &DAG) { // Promote the value if needed. switch (VA.getLocInfo()) { - default: LLVM_UNREACHABLE("Unknown loc info!"); + default: llvm_unreachable("Unknown loc info!"); case CCValAssign::Full: break; case CCValAssign::SExt: Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg); @@ -332,7 +332,7 @@ static SDValue LowerCALL(SDValue Op, SelectionDAG &DAG) { SDValue ValToStore(0, 0); unsigned ObjSize; switch (ObjectVT.getSimpleVT()) { - default: LLVM_UNREACHABLE("Unhandled argument type!"); + default: llvm_unreachable("Unhandled argument type!"); case MVT::i32: ObjSize = 4; @@ -498,7 +498,7 @@ static SDValue LowerCALL(SDValue Op, SelectionDAG &DAG) { /// condition. static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) { switch (CC) { - default: LLVM_UNREACHABLE("Unknown integer condition code!"); + default: llvm_unreachable("Unknown integer condition code!"); case ISD::SETEQ: return SPCC::ICC_E; case ISD::SETNE: return SPCC::ICC_NE; case ISD::SETLT: return SPCC::ICC_L; @@ -516,7 +516,7 @@ static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) { /// FCC condition. static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { switch (CC) { - default: LLVM_UNREACHABLE("Unknown fp condition code!"); + default: llvm_unreachable("Unknown fp condition code!"); case ISD::SETEQ: case ISD::SETOEQ: return SPCC::FCC_E; case ISD::SETNE: @@ -902,12 +902,12 @@ static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) { SDValue SparcTargetLowering:: LowerOperation(SDValue Op, SelectionDAG &DAG) { switch (Op.getOpcode()) { - default: LLVM_UNREACHABLE("Should not custom lower this!"); + default: llvm_unreachable("Should not custom lower this!"); // Frame & Return address. Currently unimplemented case ISD::RETURNADDR: return SDValue(); case ISD::FRAMEADDR: return SDValue(); case ISD::GlobalTLSAddress: - LLVM_UNREACHABLE("TLS not implemented for Sparc."); + llvm_unreachable("TLS not implemented for Sparc."); case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG); case ISD::ConstantPool: return LowerCONSTANTPOOL(Op, DAG); case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); @@ -931,7 +931,7 @@ SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, DebugLoc dl = MI->getDebugLoc(); // Figure out the conditional branch opcode to use for this select_cc. switch (MI->getOpcode()) { - default: LLVM_UNREACHABLE("Unknown SELECT_CC!"); + default: llvm_unreachable("Unknown SELECT_CC!"); case SP::SELECT_CC_Int_ICC: case SP::SELECT_CC_FP_ICC: case SP::SELECT_CC_DFP_ICC: diff --git a/lib/Target/Sparc/SparcInstrInfo.cpp b/lib/Target/Sparc/SparcInstrInfo.cpp index 451c458..af2a58a 100644 --- a/lib/Target/Sparc/SparcInstrInfo.cpp +++ b/lib/Target/Sparc/SparcInstrInfo.cpp @@ -161,7 +161,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0) .addReg(SrcReg, getKillRegState(isKill)); else - LLVM_UNREACHABLE("Can't store this register to stack slot"); + llvm_unreachable("Can't store this register to stack slot"); } void SparcInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, @@ -178,7 +178,7 @@ void SparcInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, else if (RC == SP::DFPRegsRegisterClass) Opc = SP::STDFri; else - LLVM_UNREACHABLE("Can't load this register"); + llvm_unreachable("Can't load this register"); MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)); for (unsigned i = 0, e = Addr.size(); i != e; ++i) MIB.addOperand(Addr[i]); @@ -201,7 +201,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, else if (RC == SP::DFPRegsRegisterClass) BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0); else - LLVM_UNREACHABLE("Can't load this register from stack slot"); + llvm_unreachable("Can't load this register from stack slot"); } void SparcInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, @@ -216,7 +216,7 @@ void SparcInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, else if (RC == SP::DFPRegsRegisterClass) Opc = SP::LDDFri; else - LLVM_UNREACHABLE("Can't load this register"); + llvm_unreachable("Can't load this register"); DebugLoc DL = DebugLoc::getUnknownLoc(); MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); for (unsigned i = 0, e = Addr.size(); i != e; ++i) diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp index ab3c25e..2acce3d 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.cpp +++ b/lib/Target/Sparc/SparcRegisterInfo.cpp @@ -169,27 +169,27 @@ void SparcRegisterInfo::emitEpilogue(MachineFunction &MF, } unsigned SparcRegisterInfo::getRARegister() const { - LLVM_UNREACHABLE("What is the return address register"); + llvm_unreachable("What is the return address register"); return 0; } unsigned SparcRegisterInfo::getFrameRegister(MachineFunction &MF) const { - LLVM_UNREACHABLE("What is the frame register"); + llvm_unreachable("What is the frame register"); return SP::G1; } unsigned SparcRegisterInfo::getEHExceptionRegister() const { - LLVM_UNREACHABLE("What is the exception register"); + llvm_unreachable("What is the exception register"); return 0; } unsigned SparcRegisterInfo::getEHHandlerRegister() const { - LLVM_UNREACHABLE("What is the exception handler register"); + llvm_unreachable("What is the exception handler register"); return 0; } int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { - LLVM_UNREACHABLE("What is the dwarf register number"); + llvm_unreachable("What is the dwarf register number"); return -1; } diff --git a/lib/Target/TargetAsmInfo.cpp b/lib/Target/TargetAsmInfo.cpp index 08ae2cf..eeebc27 100644 --- a/lib/Target/TargetAsmInfo.cpp +++ b/lib/Target/TargetAsmInfo.cpp @@ -278,7 +278,7 @@ TargetAsmInfo::SectionFlagsForGlobal(const GlobalValue *GV, Flags |= SectionFlags::Small; break; default: - LLVM_UNREACHABLE("Unexpected section kind!"); + llvm_unreachable("Unexpected section kind!"); } if (GV->isWeakForLinker()) @@ -388,7 +388,7 @@ TargetAsmInfo::UniqueSectionForGlobal(const GlobalValue* GV, case SectionKind::ThreadBSS: return ".gnu.linkonce.tb." + GV->getName(); default: - LLVM_UNREACHABLE("Unknown section kind"); + llvm_unreachable("Unknown section kind"); } return NULL; } diff --git a/lib/Target/TargetData.cpp b/lib/Target/TargetData.cpp index b3f2e98..3f1979b 100644 --- a/lib/Target/TargetData.cpp +++ b/lib/Target/TargetData.cpp @@ -454,7 +454,7 @@ uint64_t TargetData::getTypeSizeInBits(const Type *Ty) const { case Type::VectorTyID: return cast<VectorType>(Ty)->getBitWidth(); default: - LLVM_UNREACHABLE("TargetData::getTypeSizeInBits(): Unsupported type"); + llvm_unreachable("TargetData::getTypeSizeInBits(): Unsupported type"); break; } return 0; @@ -509,7 +509,7 @@ unsigned char TargetData::getAlignment(const Type *Ty, bool abi_or_pref) const { AlignType = VECTOR_ALIGN; break; default: - LLVM_UNREACHABLE("Bad type for getAlignment!!!"); + llvm_unreachable("Bad type for getAlignment!!!"); break; } diff --git a/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp b/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp index f160bd0..c726ccc 100644 --- a/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp +++ b/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp @@ -55,7 +55,7 @@ void X86ATTAsmPrinter::PrintPICBaseSymbol() const { else if (Subtarget->isTargetELF()) O << ".Lllvm$" << getFunctionNumber() << ".$piclabel"; else - LLVM_UNREACHABLE("Don't know how to print PIC label!"); + llvm_unreachable("Don't know how to print PIC label!"); } /// PrintUnmangledNameSafely - Print out the printable characters in the name. @@ -155,7 +155,7 @@ void X86ATTAsmPrinter::decorateName(std::string &Name, } break; default: - LLVM_UNREACHABLE("Unsupported DecorationStyle"); + llvm_unreachable("Unsupported DecorationStyle"); } } @@ -167,7 +167,7 @@ void X86ATTAsmPrinter::emitFunctionHeader(const MachineFunction &MF) { SwitchToSection(TAI->SectionForGlobal(F)); switch (F->getLinkage()) { - default: LLVM_UNREACHABLE("Unknown linkage type!"); + default: llvm_unreachable("Unknown linkage type!"); case Function::InternalLinkage: // Symbols default to internal. case Function::PrivateLinkage: EmitAlignment(FnAlign, F); @@ -292,7 +292,7 @@ bool X86ATTAsmPrinter::runOnMachineFunction(MachineFunction &MF) { /// which print to a label with various suffixes for relocation types etc. void X86ATTAsmPrinter::printSymbolOperand(const MachineOperand &MO) { switch (MO.getType()) { - default: LLVM_UNREACHABLE("unknown symbol type!"); + default: llvm_unreachable("unknown symbol type!"); case MachineOperand::MO_JumpTableIndex: O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber() << '_' << MO.getIndex(); @@ -366,7 +366,7 @@ void X86ATTAsmPrinter::printSymbolOperand(const MachineOperand &MO) { switch (MO.getTargetFlags()) { default: - LLVM_UNREACHABLE("Unknown target flag on GV operand"); + llvm_unreachable("Unknown target flag on GV operand"); case X86II::MO_NO_FLAG: // No flag. break; case X86II::MO_DARWIN_NONLAZY: @@ -404,7 +404,7 @@ void X86ATTAsmPrinter::printSymbolOperand(const MachineOperand &MO) { void X86ATTAsmPrinter::print_pcrel_imm(const MachineInstr *MI, unsigned OpNo) { const MachineOperand &MO = MI->getOperand(OpNo); switch (MO.getType()) { - default: LLVM_UNREACHABLE("Unknown pcrel immediate operand"); + default: llvm_unreachable("Unknown pcrel immediate operand"); case MachineOperand::MO_Immediate: O << MO.getImm(); return; @@ -426,7 +426,7 @@ void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo, const char *Modifier) { const MachineOperand &MO = MI->getOperand(OpNo); switch (MO.getType()) { - default: LLVM_UNREACHABLE("unknown operand type!"); + default: llvm_unreachable("unknown operand type!"); case MachineOperand::MO_Register: { assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && "Virtual registers should not make it this far!"); @@ -735,7 +735,7 @@ void X86ATTAsmPrinter::printMachineInstruction(const MachineInstr *MI) { } else if (MO.isMBB()) { MCOp.MakeMBBLabel(getFunctionNumber(), MO.getMBB()->getNumber()); } else { - LLVM_UNREACHABLE("Unimp"); + llvm_unreachable("Unimp"); } TmpInst.addOperand(MCOp); @@ -887,7 +887,7 @@ void X86ATTAsmPrinter::printModuleLevelGV(const GlobalVariable* GVar) { case GlobalValue::InternalLinkage: break; default: - LLVM_UNREACHABLE("Unknown linkage type!"); + llvm_unreachable("Unknown linkage type!"); } EmitAlignment(Align, GVar); diff --git a/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp b/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp index c3780d9..e0fa83a 100644 --- a/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp +++ b/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp @@ -28,7 +28,7 @@ using namespace llvm; void X86ATTAsmPrinter::printSSECC(const MCInst *MI, unsigned Op) { switch (MI->getOperand(Op).getImm()) { - default: LLVM_UNREACHABLE("Invalid ssecc argument!"); + default: llvm_unreachable("Invalid ssecc argument!"); case 0: O << "eq"; break; case 1: O << "lt"; break; case 2: O << "le"; break; @@ -42,7 +42,7 @@ void X86ATTAsmPrinter::printSSECC(const MCInst *MI, unsigned Op) { void X86ATTAsmPrinter::printPICLabel(const MCInst *MI, unsigned Op) { - LLVM_UNREACHABLE("This is only used for MOVPC32r," + llvm_unreachable("This is only used for MOVPC32r," "should lower before asm printing!"); } @@ -61,7 +61,7 @@ void X86ATTAsmPrinter::print_pcrel_imm(const MCInst *MI, unsigned OpNo) { O << TAI->getPrivateGlobalPrefix() << "BB" << Op.getMBBLabelFunction() << '_' << Op.getMBBLabelBlock(); else - LLVM_UNREACHABLE("Unknown pcrel immediate operand"); + llvm_unreachable("Unknown pcrel immediate operand"); } @@ -104,7 +104,7 @@ void X86ATTAsmPrinter::printLeaMemReference(const MCInst *MI, unsigned Op) { if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) O << DispVal; } else { - LLVM_UNREACHABLE("non-immediate displacement for LEA?"); + llvm_unreachable("non-immediate displacement for LEA?"); //assert(DispSpec.isGlobal() || DispSpec.isCPI() || // DispSpec.isJTI() || DispSpec.isSymbol()); //printOperand(MI, Op+3, "mem"); diff --git a/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp b/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp index 793616e..9890fdd 100644 --- a/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp +++ b/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp @@ -115,7 +115,7 @@ void X86IntelAsmPrinter::decorateName(std::string &Name, break; default: - LLVM_UNREACHABLE("Unsupported DecorationStyle"); + llvm_unreachable("Unsupported DecorationStyle"); } } @@ -144,7 +144,7 @@ bool X86IntelAsmPrinter::runOnMachineFunction(MachineFunction &MF) { SwitchToTextSection("_text", F); switch (F->getLinkage()) { - default: LLVM_UNREACHABLE("Unsupported linkage type!"); + default: llvm_unreachable("Unsupported linkage type!"); case Function::PrivateLinkage: case Function::InternalLinkage: EmitAlignment(FnAlign); @@ -268,7 +268,7 @@ void X86IntelAsmPrinter::printOp(const MachineOperand &MO, void X86IntelAsmPrinter::print_pcrel_imm(const MachineInstr *MI, unsigned OpNo){ const MachineOperand &MO = MI->getOperand(OpNo); switch (MO.getType()) { - default: LLVM_UNREACHABLE("Unknown pcrel immediate operand"); + default: llvm_unreachable("Unknown pcrel immediate operand"); case MachineOperand::MO_Immediate: O << MO.getImm(); return; @@ -520,7 +520,7 @@ bool X86IntelAsmPrinter::doFinalization(Module &M) { SwitchToSection(TAI->getDataSection()); break; default: - LLVM_UNREACHABLE("Unknown linkage type!"); + llvm_unreachable("Unknown linkage type!"); } if (!bCustomSegment) diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp index acaeea3..30bbc5c 100644 --- a/lib/Target/X86/X86CodeEmitter.cpp +++ b/lib/Target/X86/X86CodeEmitter.cpp @@ -335,7 +335,7 @@ void Emitter<CodeEmitter>::emitDisplacementField(const MachineOperand *RelocOp, unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_picrel_word; emitJumpTableAddress(RelocOp->getIndex(), rt, PCAdj); } else { - LLVM_UNREACHABLE("Unknown value to relocate!"); + llvm_unreachable("Unknown value to relocate!"); } } @@ -478,7 +478,7 @@ void Emitter<CodeEmitter>::emitInstruction( case X86II::GS: MCE.emitByte(0x65); break; - default: LLVM_UNREACHABLE("Invalid segment!"); + default: llvm_unreachable("Invalid segment!"); case 0: break; // No segment override! } @@ -513,7 +513,7 @@ void Emitter<CodeEmitter>::emitInstruction( (((Desc->TSFlags & X86II::Op0Mask)-X86II::D8) >> X86II::Op0Shift)); break; // Two-byte opcode prefix - default: LLVM_UNREACHABLE("Invalid prefix!"); + default: llvm_unreachable("Invalid prefix!"); case 0: break; // No prefix! } @@ -548,13 +548,13 @@ void Emitter<CodeEmitter>::emitInstruction( unsigned char BaseOpcode = II->getBaseOpcodeFor(Desc); switch (Desc->TSFlags & X86II::FormMask) { - default: LLVM_UNREACHABLE("Unknown FormMask value in X86 MachineCodeEmitter!"); + default: llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!"); case X86II::Pseudo: // Remember the current PC offset, this is the PIC relocation // base address. switch (Opcode) { default: - LLVM_UNREACHABLE("psuedo instructions should be removed before code emission"); + llvm_unreachable("psuedo instructions should be removed before code emission"); break; case TargetInstrInfo::INLINEASM: { // We allow inline assembler nodes with empty bodies - they can @@ -620,7 +620,7 @@ void Emitter<CodeEmitter>::emitInstruction( } else emitConstant(MO.getImm(), X86InstrInfo::sizeOfImm(Desc)); } else { - LLVM_UNREACHABLE("Unknown RawFrm operand!"); + llvm_unreachable("Unknown RawFrm operand!"); } } break; @@ -811,7 +811,7 @@ void Emitter<CodeEmitter>::emitInstruction( #ifndef NDEBUG cerr << "Cannot encode: " << MI << "\n"; #endif - llvm_unreachable(); + llvm_unreachable(0); } } diff --git a/lib/Target/X86/X86ELFWriterInfo.cpp b/lib/Target/X86/X86ELFWriterInfo.cpp index 9be7021..a26fe8c 100644 --- a/lib/Target/X86/X86ELFWriterInfo.cpp +++ b/lib/Target/X86/X86ELFWriterInfo.cpp @@ -43,7 +43,7 @@ unsigned X86ELFWriterInfo::getRelocationType(unsigned MachineRelTy) const { return R_X86_64_64; case X86::reloc_picrel_word: default: - LLVM_UNREACHABLE("unknown relocation type"); + llvm_unreachable("unknown relocation type"); } } else { switch(MachineRelTy) { @@ -54,7 +54,7 @@ unsigned X86ELFWriterInfo::getRelocationType(unsigned MachineRelTy) const { case X86::reloc_absolute_dword: case X86::reloc_picrel_word: default: - LLVM_UNREACHABLE("unknown relocation type"); + llvm_unreachable("unknown relocation type"); } } return 0; @@ -66,7 +66,7 @@ long int X86ELFWriterInfo::getAddendForRelTy(unsigned RelTy) const { case R_X86_64_PC32: return -4; break; default: - LLVM_UNREACHABLE("unknown x86 relocation type"); + llvm_unreachable("unknown x86 relocation type"); } } return 0; diff --git a/lib/Target/X86/X86FastISel.cpp b/lib/Target/X86/X86FastISel.cpp index 2b3304d..11919d9 100644 --- a/lib/Target/X86/X86FastISel.cpp +++ b/lib/Target/X86/X86FastISel.cpp @@ -1319,7 +1319,7 @@ bool X86FastISel::X86SelectCall(Instruction *I) { // Promote the value if needed. switch (VA.getLocInfo()) { - default: LLVM_UNREACHABLE("Unknown loc info!"); + default: llvm_unreachable("Unknown loc info!"); case CCValAssign::Full: break; case CCValAssign::SExt: { bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), diff --git a/lib/Target/X86/X86FloatingPoint.cpp b/lib/Target/X86/X86FloatingPoint.cpp index c15e348..14bffdc 100644 --- a/lib/Target/X86/X86FloatingPoint.cpp +++ b/lib/Target/X86/X86FloatingPoint.cpp @@ -256,7 +256,7 @@ bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) { case X86II::CompareFP: handleCompareFP(I); break; case X86II::CondMovFP: handleCondMovFP(I); break; case X86II::SpecialFP: handleSpecialFP(I); break; - default: LLVM_UNREACHABLE("Unknown FP Type!"); + default: llvm_unreachable("Unknown FP Type!"); } // Check to see if any of the values defined by this instruction are dead @@ -946,7 +946,7 @@ void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) { MachineInstr *MI = I; DebugLoc dl = MI->getDebugLoc(); switch (MI->getOpcode()) { - default: LLVM_UNREACHABLE("Unknown SpecialFP instruction!"); + default: llvm_unreachable("Unknown SpecialFP instruction!"); case X86::FpGET_ST0_32:// Appears immediately after a call returning FP type! case X86::FpGET_ST0_64:// Appears immediately after a call returning FP type! case X86::FpGET_ST0_80:// Appears immediately after a call returning FP type! diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp index 8aa627f..296a4d3 100644 --- a/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -1462,7 +1462,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) { bool isSigned = Opcode == ISD::SMUL_LOHI; if (!isSigned) switch (NVT.getSimpleVT()) { - default: LLVM_UNREACHABLE("Unsupported VT!"); + default: llvm_unreachable("Unsupported VT!"); case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break; case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break; case MVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break; @@ -1470,7 +1470,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) { } else switch (NVT.getSimpleVT()) { - default: LLVM_UNREACHABLE("Unsupported VT!"); + default: llvm_unreachable("Unsupported VT!"); case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break; case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break; case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break; @@ -1479,7 +1479,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) { unsigned LoReg, HiReg; switch (NVT.getSimpleVT()) { - default: LLVM_UNREACHABLE("Unsupported VT!"); + default: llvm_unreachable("Unsupported VT!"); case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; break; case MVT::i16: LoReg = X86::AX; HiReg = X86::DX; break; case MVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break; @@ -1568,7 +1568,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) { bool isSigned = Opcode == ISD::SDIVREM; if (!isSigned) switch (NVT.getSimpleVT()) { - default: LLVM_UNREACHABLE("Unsupported VT!"); + default: llvm_unreachable("Unsupported VT!"); case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break; case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break; case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break; @@ -1576,7 +1576,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) { } else switch (NVT.getSimpleVT()) { - default: LLVM_UNREACHABLE("Unsupported VT!"); + default: llvm_unreachable("Unsupported VT!"); case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break; case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break; case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break; @@ -1586,7 +1586,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) { unsigned LoReg, HiReg; unsigned ClrOpcode, SExtOpcode; switch (NVT.getSimpleVT()) { - default: LLVM_UNREACHABLE("Unsupported VT!"); + default: llvm_unreachable("Unsupported VT!"); case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; ClrOpcode = 0; diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 1e79c4d..a2fedaf 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -1426,7 +1426,7 @@ X86TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) { } } } else { - LLVM_UNREACHABLE("Unknown argument type!"); + llvm_unreachable("Unknown argument type!"); } unsigned Reg = DAG.getMachineFunction().addLiveIn(VA.getLocReg(), RC); @@ -1721,7 +1721,7 @@ SDValue X86TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) { // Promote the value if needed. switch (VA.getLocInfo()) { - default: LLVM_UNREACHABLE("Unknown loc info!"); + default: llvm_unreachable("Unknown loc info!"); case CCValAssign::Full: break; case CCValAssign::SExt: Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); @@ -2167,7 +2167,7 @@ static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, } switch (SetCCOpcode) { - default: LLVM_UNREACHABLE("Invalid integer condition!"); + default: llvm_unreachable("Invalid integer condition!"); case ISD::SETEQ: return X86::COND_E; case ISD::SETGT: return X86::COND_G; case ISD::SETGE: return X86::COND_GE; @@ -2207,7 +2207,7 @@ static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, // 1 | 0 | 0 | X == Y // 1 | 1 | 1 | unordered switch (SetCCOpcode) { - default: LLVM_UNREACHABLE("Condcode should be pre-legalized away"); + default: llvm_unreachable("Condcode should be pre-legalized away"); case ISD::SETUEQ: case ISD::SETEQ: return X86::COND_E; case ISD::SETOLT: // flipped @@ -4715,7 +4715,7 @@ X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) { Subtarget->is64Bit()); } - LLVM_UNREACHABLE("Unreachable"); + llvm_unreachable("Unreachable"); return SDValue(); } @@ -5038,7 +5038,7 @@ FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) { unsigned Opc; switch (DstTy.getSimpleVT()) { - default: LLVM_UNREACHABLE("Invalid FP_TO_SINT to lower!"); + default: llvm_unreachable("Invalid FP_TO_SINT to lower!"); case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; @@ -5461,7 +5461,7 @@ SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) { NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8)); return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ); } - LLVM_UNREACHABLE("Illegal FP comparison"); + llvm_unreachable("Illegal FP comparison"); } // Handle all other FP comparisons here. return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8)); @@ -6247,7 +6247,7 @@ X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) { case Intrinsic::x86_mmx_psrai_d: NewIntNo = Intrinsic::x86_mmx_psra_d; break; - default: LLVM_UNREACHABLE("Impossible intrinsic"); // Can't reach here. + default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. } break; } @@ -6397,7 +6397,7 @@ SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op, switch (CC) { default: - LLVM_UNREACHABLE("Unsupported calling convention"); + llvm_unreachable("Unsupported calling convention"); case CallingConv::C: case CallingConv::X86_StdCall: { // Pass 'nest' parameter in ECX. @@ -6646,7 +6646,7 @@ SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) { DebugLoc dl = Op.getDebugLoc(); switch (Op.getOpcode()) { - default: LLVM_UNREACHABLE("Unknown ovf instruction!"); + default: llvm_unreachable("Unknown ovf instruction!"); case ISD::SADDO: // A subtract of one will be selected as a INC. Note that INC doesn't // set CF, so we can't do this for UADDO. @@ -6768,7 +6768,7 @@ SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) { /// SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { switch (Op.getOpcode()) { - default: LLVM_UNREACHABLE("Should not custom lower this!"); + default: llvm_unreachable("Should not custom lower this!"); case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); @@ -7616,7 +7616,7 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, // Get the X86 opcode to use. unsigned Opc; switch (MI->getOpcode()) { - default: LLVM_UNREACHABLE("illegal opcode!"); + default: llvm_unreachable("illegal opcode!"); case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; @@ -8355,7 +8355,7 @@ static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, SDValue ValOp = N->getOperand(0); switch (N->getOpcode()) { default: - LLVM_UNREACHABLE("Unknown shift opcode!"); + llvm_unreachable("Unknown shift opcode!"); break; case ISD::SHL: if (VT == MVT::v2i64) diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index 06e2b8d..6c06e58 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -1300,7 +1300,7 @@ X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { unsigned Opc; unsigned Size; switch (MI->getOpcode()) { - default: LLVM_UNREACHABLE("Unreachable!"); + default: llvm_unreachable("Unreachable!"); case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break; case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break; case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break; @@ -1455,7 +1455,7 @@ static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) { unsigned X86::GetCondBranchFromCond(X86::CondCode CC) { switch (CC) { - default: LLVM_UNREACHABLE("Illegal condition code!"); + default: llvm_unreachable("Illegal condition code!"); case X86::COND_E: return X86::JE; case X86::COND_NE: return X86::JNE; case X86::COND_L: return X86::JL; @@ -1479,7 +1479,7 @@ unsigned X86::GetCondBranchFromCond(X86::CondCode CC) { /// e.g. turning COND_E to COND_NE. X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) { switch (CC) { - default: LLVM_UNREACHABLE("Illegal condition code!"); + default: llvm_unreachable("Illegal condition code!"); case X86::COND_E: return X86::COND_NE; case X86::COND_NE: return X86::COND_E; case X86::COND_L: return X86::COND_GE; @@ -1885,7 +1885,7 @@ static unsigned getStoreRegOpcode(unsigned SrcReg, } else if (RC == &X86::VR64RegClass) { Opc = X86::MMX_MOVQ64mr; } else { - LLVM_UNREACHABLE("Unknown regclass"); + llvm_unreachable("Unknown regclass"); } return Opc; @@ -1977,7 +1977,7 @@ static unsigned getLoadRegOpcode(unsigned DestReg, } else if (RC == &X86::VR64RegClass) { Opc = X86::MMX_MOVQ64rm; } else { - LLVM_UNREACHABLE("Unknown regclass"); + llvm_unreachable("Unknown regclass"); } return Opc; @@ -2645,7 +2645,7 @@ unsigned X86InstrInfo::sizeOfImm(const TargetInstrDesc *Desc) { case X86II::Imm16: return 2; case X86II::Imm32: return 4; case X86II::Imm64: return 8; - default: LLVM_UNREACHABLE("Immediate size not set!"); + default: llvm_unreachable("Immediate size not set!"); return 0; } } @@ -2830,7 +2830,7 @@ static unsigned getDisplacementFieldSize(const MachineOperand *RelocOp) { } else if (RelocOp->isJTI()) { FinalSize += sizeJumpTableAddress(false); } else { - LLVM_UNREACHABLE("Unknown value to relocate!"); + llvm_unreachable("Unknown value to relocate!"); } return FinalSize; } @@ -2927,7 +2927,7 @@ static unsigned GetInstSizeWithDesc(const MachineInstr &MI, case X86II::GS: ++FinalSize; break; - default: LLVM_UNREACHABLE("Invalid segment!"); + default: llvm_unreachable("Invalid segment!"); case 0: break; // No segment override! } @@ -2960,7 +2960,7 @@ static unsigned GetInstSizeWithDesc(const MachineInstr &MI, case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF: ++FinalSize; break; // Two-byte opcode prefix - default: LLVM_UNREACHABLE("Invalid prefix!"); + default: llvm_unreachable("Invalid prefix!"); case 0: break; // No prefix! } @@ -2994,7 +2994,7 @@ static unsigned GetInstSizeWithDesc(const MachineInstr &MI, --NumOps; switch (Desc->TSFlags & X86II::FormMask) { - default: LLVM_UNREACHABLE("Unknown FormMask value in X86 MachineCodeEmitter!"); + default: llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!"); case X86II::Pseudo: // Remember the current PC offset, this is the PIC relocation // base address. @@ -3039,7 +3039,7 @@ static unsigned GetInstSizeWithDesc(const MachineInstr &MI, } else if (MO.isImm()) { FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc)); } else { - LLVM_UNREACHABLE("Unknown RawFrm operand!"); + llvm_unreachable("Unknown RawFrm operand!"); } } break; diff --git a/lib/Target/X86/X86JITInfo.cpp b/lib/Target/X86/X86JITInfo.cpp index 4cc27ef..24e391e 100644 --- a/lib/Target/X86/X86JITInfo.cpp +++ b/lib/Target/X86/X86JITInfo.cpp @@ -322,7 +322,7 @@ extern "C" { #else // Not an i386 host void X86CompilationCallback() { - LLVM_UNREACHABLE("Cannot call X86CompilationCallback() on a non-x86 arch!"); + llvm_unreachable("Cannot call X86CompilationCallback() on a non-x86 arch!"); } #endif } @@ -554,7 +554,7 @@ char* X86JITInfo::allocateThreadLocalMemory(size_t size) { TLSOffset -= size; return TLSOffset; #else - LLVM_UNREACHABLE("Cannot allocate thread local storage on this arch!"); + llvm_unreachable("Cannot allocate thread local storage on this arch!"); return 0; #endif } diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index 3ae758b..437986f 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -147,7 +147,7 @@ unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) { default: assert(isVirtualRegister(RegNo) && "Unknown physical register!"); - LLVM_UNREACHABLE("Register allocator hasn't allocated reg correctly yet!"); + llvm_unreachable("Register allocator hasn't allocated reg correctly yet!"); return 0; } } @@ -951,7 +951,7 @@ void X86RegisterInfo::emitEpilogue(MachineFunction &MF, case X86::TAILJMPr: case X86::TAILJMPm: break; // These are ok default: - LLVM_UNREACHABLE("Can only insert epilog into returning blocks"); + llvm_unreachable("Can only insert epilog into returning blocks"); } // Get the number of bytes to allocate from the FrameInfo @@ -1104,12 +1104,12 @@ void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) } unsigned X86RegisterInfo::getEHExceptionRegister() const { - LLVM_UNREACHABLE("What is the exception register"); + llvm_unreachable("What is the exception register"); return 0; } unsigned X86RegisterInfo::getEHHandlerRegister() const { - LLVM_UNREACHABLE("What is the exception handler register"); + llvm_unreachable("What is the exception handler register"); return 0; } diff --git a/lib/Target/X86/X86TargetAsmInfo.cpp b/lib/Target/X86/X86TargetAsmInfo.cpp index 5a60bce..c33b765 100644 --- a/lib/Target/X86/X86TargetAsmInfo.cpp +++ b/lib/Target/X86/X86TargetAsmInfo.cpp @@ -283,7 +283,7 @@ X86COFFTargetAsmInfo::UniqueSectionForGlobal(const GlobalValue* GV, case SectionKind::RODataMergeStr: return ".rdata$linkonce" + GV->getName(); default: - LLVM_UNREACHABLE("Unknown section kind"); + llvm_unreachable("Unknown section kind"); } return NULL; } diff --git a/lib/Target/XCore/XCoreAsmPrinter.cpp b/lib/Target/XCore/XCoreAsmPrinter.cpp index 5234a9b..5874294 100644 --- a/lib/Target/XCore/XCoreAsmPrinter.cpp +++ b/lib/Target/XCore/XCoreAsmPrinter.cpp @@ -204,13 +204,13 @@ emitGlobal(const GlobalVariable *GV) case GlobalValue::PrivateLinkage: break; case GlobalValue::GhostLinkage: - LLVM_UNREACHABLE("Should not have any unmaterialized functions!"); + llvm_unreachable("Should not have any unmaterialized functions!"); case GlobalValue::DLLImportLinkage: - LLVM_UNREACHABLE("DLLImport linkage is not supported by this target!"); + llvm_unreachable("DLLImport linkage is not supported by this target!"); case GlobalValue::DLLExportLinkage: - LLVM_UNREACHABLE("DLLExport linkage is not supported by this target!"); + llvm_unreachable("DLLExport linkage is not supported by this target!"); default: - LLVM_UNREACHABLE("Unknown linkage type!"); + llvm_unreachable("Unknown linkage type!"); } EmitAlignment(Align, GV, 2); @@ -255,7 +255,7 @@ emitFunctionStart(MachineFunction &MF) O << "\t.cc_top " << CurrentFnName << ".function," << CurrentFnName << "\n"; switch (F->getLinkage()) { - default: LLVM_UNREACHABLE("Unknown linkage type!"); + default: llvm_unreachable("Unknown linkage type!"); case Function::InternalLinkage: // Symbols default to internal. case Function::PrivateLinkage: break; @@ -358,7 +358,7 @@ void XCoreAsmPrinter::printOperand(const MachineInstr *MI, int opNum) { if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) O << TM.getRegisterInfo()->get(MO.getReg()).AsmName; else - LLVM_UNREACHABLE("not implemented"); + llvm_unreachable("not implemented"); break; case MachineOperand::MO_Immediate: O << MO.getImm(); @@ -381,7 +381,7 @@ void XCoreAsmPrinter::printOperand(const MachineInstr *MI, int opNum) { << '_' << MO.getIndex(); break; default: - LLVM_UNREACHABLE("not implemented"); + llvm_unreachable("not implemented"); } } @@ -410,7 +410,7 @@ void XCoreAsmPrinter::printMachineInstruction(const MachineInstr *MI) { if (printInstruction(MI)) { return; } - LLVM_UNREACHABLE("Unhandled instruction in asm writer!"); + llvm_unreachable("Unhandled instruction in asm writer!"); } bool XCoreAsmPrinter::doInitialization(Module &M) { diff --git a/lib/Target/XCore/XCoreISelLowering.cpp b/lib/Target/XCore/XCoreISelLowering.cpp index c2cc09c..f6a181e 100644 --- a/lib/Target/XCore/XCoreISelLowering.cpp +++ b/lib/Target/XCore/XCoreISelLowering.cpp @@ -167,7 +167,7 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) { case ISD::SUB: return ExpandADDSUB(Op.getNode(), DAG); case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); default: - LLVM_UNREACHABLE("unimplemented operand"); + llvm_unreachable("unimplemented operand"); return SDValue(); } } @@ -179,7 +179,7 @@ void XCoreTargetLowering::ReplaceNodeResults(SDNode *N, SelectionDAG &DAG) { switch (N->getOpcode()) { default: - LLVM_UNREACHABLE("Don't know how to custom expand this!"); + llvm_unreachable("Don't know how to custom expand this!"); return; case ISD::ADD: case ISD::SUB: @@ -266,7 +266,7 @@ LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal()); } if (! GVar) { - LLVM_UNREACHABLE("Thread local object not a GlobalVariable?"); + llvm_unreachable("Thread local object not a GlobalVariable?"); return SDValue(); } const Type *Ty = cast<PointerType>(GV->getType())->getElementType(); @@ -275,7 +275,7 @@ LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) cerr << "Size of thread local object " << GVar->getName() << " is unknown\n"; #endif - llvm_unreachable(); + llvm_unreachable(0); } SDValue base = getGlobalAddressWrapper(GA, GV, DAG); const TargetData *TD = TM.getTargetData(); @@ -292,7 +292,7 @@ LowerConstantPool(SDValue Op, SelectionDAG &DAG) // FIXME there isn't really debug info here DebugLoc dl = CP->getDebugLoc(); if (Subtarget.isXS1A()) { - LLVM_UNREACHABLE("Lowering of constant pool unimplemented"); + llvm_unreachable("Lowering of constant pool unimplemented"); return SDValue(); } else { MVT PtrVT = Op.getValueType(); @@ -356,7 +356,7 @@ ExpandADDSUB(SDNode *N, SelectionDAG &DAG) SDValue XCoreTargetLowering:: LowerVAARG(SDValue Op, SelectionDAG &DAG) { - LLVM_UNREACHABLE("unimplemented"); + llvm_unreachable("unimplemented"); // FIX Arguments passed by reference need a extra dereference. SDNode *Node = Op.getNode(); DebugLoc dl = Node->getDebugLoc(); @@ -426,7 +426,7 @@ LowerCALL(SDValue Op, SelectionDAG &DAG) switch (CallingConv) { default: - LLVM_UNREACHABLE("Unsupported calling convention"); + llvm_unreachable("Unsupported calling convention"); case CallingConv::Fast: case CallingConv::C: return LowerCCCCallTo(Op, DAG, CallingConv); @@ -474,7 +474,7 @@ LowerCCCCallTo(SDValue Op, SelectionDAG &DAG, unsigned CC) // Promote the value if needed. switch (VA.getLocInfo()) { - default: LLVM_UNREACHABLE("Unknown loc info!"); + default: llvm_unreachable("Unknown loc info!"); case CCValAssign::Full: break; case CCValAssign::SExt: Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); @@ -607,7 +607,7 @@ LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) switch(CC) { default: - LLVM_UNREACHABLE("Unsupported calling convention"); + llvm_unreachable("Unsupported calling convention"); case CallingConv::C: case CallingConv::Fast: return LowerCCCArguments(Op, DAG); @@ -655,7 +655,7 @@ LowerCCCArguments(SDValue Op, SelectionDAG &DAG) cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: " << RegVT.getSimpleVT() << "\n"; #endif - llvm_unreachable(); + llvm_unreachable(0); } case MVT::i32: unsigned VReg = RegInfo.createVirtualRegister( diff --git a/lib/Target/XCore/XCoreInstrInfo.cpp b/lib/Target/XCore/XCoreInstrInfo.cpp index ea35504..ad47ac2 100644 --- a/lib/Target/XCore/XCoreInstrInfo.cpp +++ b/lib/Target/XCore/XCoreInstrInfo.cpp @@ -187,7 +187,7 @@ static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc) static inline unsigned GetCondBranchFromCond(XCore::CondCode CC) { switch (CC) { - default: LLVM_UNREACHABLE("Illegal condition code!"); + default: llvm_unreachable("Illegal condition code!"); case XCore::COND_TRUE : return XCore::BRFT_lru6; case XCore::COND_FALSE : return XCore::BRFF_lru6; } @@ -198,7 +198,7 @@ static inline unsigned GetCondBranchFromCond(XCore::CondCode CC) static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC) { switch (CC) { - default: LLVM_UNREACHABLE("Illegal condition code!"); + default: llvm_unreachable("Illegal condition code!"); case XCore::COND_TRUE : return XCore::COND_FALSE; case XCore::COND_FALSE : return XCore::COND_TRUE; } @@ -408,7 +408,7 @@ void XCoreInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const { - LLVM_UNREACHABLE("unimplemented"); + llvm_unreachable("unimplemented"); } void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, @@ -428,7 +428,7 @@ void XCoreInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const { - LLVM_UNREACHABLE("unimplemented"); + llvm_unreachable("unimplemented"); } bool XCoreInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, diff --git a/lib/Target/XCore/XCoreRegisterInfo.cpp b/lib/Target/XCore/XCoreRegisterInfo.cpp index 7773064..8bdfcdc 100644 --- a/lib/Target/XCore/XCoreRegisterInfo.cpp +++ b/lib/Target/XCore/XCoreRegisterInfo.cpp @@ -148,7 +148,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, cerr << "eliminateCallFramePseudoInstr size too big: " << Amount << "\n"; #endif - llvm_unreachable(); + llvm_unreachable(0); } MachineInstr *New; @@ -257,7 +257,7 @@ void XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, .addReg(ScratchReg, RegState::Kill); break; default: - LLVM_UNREACHABLE("Unexpected Opcode"); + llvm_unreachable("Unexpected Opcode"); } } else { switch (MI.getOpcode()) { @@ -278,7 +278,7 @@ void XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, .addImm(Offset); break; default: - LLVM_UNREACHABLE("Unexpected Opcode"); + llvm_unreachable("Unexpected Opcode"); } } } else { @@ -309,7 +309,7 @@ void XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, .addImm(Offset); break; default: - LLVM_UNREACHABLE("Unexpected Opcode"); + llvm_unreachable("Unexpected Opcode"); } } // Erase old instruction. diff --git a/lib/Transforms/IPO/GlobalOpt.cpp b/lib/Transforms/IPO/GlobalOpt.cpp index 1b8db42..398f78a 100644 --- a/lib/Transforms/IPO/GlobalOpt.cpp +++ b/lib/Transforms/IPO/GlobalOpt.cpp @@ -883,7 +883,7 @@ static GlobalVariable *OptimizeGlobalAddressOfMalloc(GlobalVariable *GV, Value *LV = new LoadInst(InitBool, InitBool->getName()+".val", CI); InitBoolUsed = true; switch (CI->getPredicate()) { - default: LLVM_UNREACHABLE("Unknown ICmp Predicate!"); + default: llvm_unreachable("Unknown ICmp Predicate!"); case ICmpInst::ICMP_ULT: case ICmpInst::ICMP_SLT: LV = Context->getConstantIntFalse(); // X < null -> always false @@ -1164,7 +1164,7 @@ static Value *GetHeapSROAValue(Value *V, unsigned FieldNo, PN->getName()+".f"+utostr(FieldNo), PN); PHIsToRewrite.push_back(std::make_pair(PN, FieldNo)); } else { - LLVM_UNREACHABLE("Unknown usable value"); + llvm_unreachable("Unknown usable value"); Result = 0; } @@ -2057,7 +2057,7 @@ static Constant *EvaluateStoreInto(Constant *Init, Constant *Val, for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) Elts.push_back(Context->getUndef(STy->getElementType(i))); } else { - LLVM_UNREACHABLE("This code is out of sync with " + llvm_unreachable("This code is out of sync with " " ConstantFoldLoadThroughGEPConstantExpr"); } @@ -2085,7 +2085,7 @@ static Constant *EvaluateStoreInto(Constant *Init, Constant *Val, Constant *Elt = Context->getUndef(ATy->getElementType()); Elts.assign(ATy->getNumElements(), Elt); } else { - LLVM_UNREACHABLE("This code is out of sync with " + llvm_unreachable("This code is out of sync with " " ConstantFoldLoadThroughGEPConstantExpr"); } diff --git a/lib/Transforms/IPO/MergeFunctions.cpp b/lib/Transforms/IPO/MergeFunctions.cpp index 31e36d8..9cc4daa 100644 --- a/lib/Transforms/IPO/MergeFunctions.cpp +++ b/lib/Transforms/IPO/MergeFunctions.cpp @@ -129,7 +129,7 @@ static bool isEquivalentType(const Type *Ty1, const Type *Ty2) { return false; default: - LLVM_UNREACHABLE("Unknown type!"); + llvm_unreachable("Unknown type!"); return false; case Type::PointerTyID: { @@ -470,7 +470,7 @@ static LinkageCategory categorize(const Function *F) { return ExternalStrong; } - LLVM_UNREACHABLE("Unknown LinkageType."); + llvm_unreachable("Unknown LinkageType."); return ExternalWeak; } @@ -576,7 +576,7 @@ static bool fold(std::vector<Function *> &FnVec, unsigned i, unsigned j) { case Internal: switch (catG) { case ExternalStrong: - llvm_unreachable(); + llvm_unreachable(0); // fall-through case ExternalWeak: if (F->hasAddressTaken()) diff --git a/lib/Transforms/Instrumentation/RSProfiling.cpp b/lib/Transforms/Instrumentation/RSProfiling.cpp index 51a0bae..36b4464 100644 --- a/lib/Transforms/Instrumentation/RSProfiling.cpp +++ b/lib/Transforms/Instrumentation/RSProfiling.cpp @@ -408,7 +408,7 @@ Value* ProfilerRS::Translate(Value* v) { TransCache[v] = v; return v; } - LLVM_UNREACHABLE("Value not handled"); + llvm_unreachable("Value not handled"); return 0; } diff --git a/lib/Transforms/Scalar/GVN.cpp b/lib/Transforms/Scalar/GVN.cpp index f0d131c..e7be985 100644 --- a/lib/Transforms/Scalar/GVN.cpp +++ b/lib/Transforms/Scalar/GVN.cpp @@ -202,7 +202,7 @@ template <> struct DenseMapInfo<Expression> { Expression::ExpressionOpcode ValueTable::getOpcode(BinaryOperator* BO) { switch(BO->getOpcode()) { default: // THIS SHOULD NEVER HAPPEN - LLVM_UNREACHABLE("Binary operator with unknown opcode?"); + llvm_unreachable("Binary operator with unknown opcode?"); case Instruction::Add: return Expression::ADD; case Instruction::FAdd: return Expression::FADD; case Instruction::Sub: return Expression::SUB; @@ -228,7 +228,7 @@ Expression::ExpressionOpcode ValueTable::getOpcode(CmpInst* C) { if (isa<ICmpInst>(C)) { switch (C->getPredicate()) { default: // THIS SHOULD NEVER HAPPEN - LLVM_UNREACHABLE("Comparison with unknown predicate?"); + llvm_unreachable("Comparison with unknown predicate?"); case ICmpInst::ICMP_EQ: return Expression::ICMPEQ; case ICmpInst::ICMP_NE: return Expression::ICMPNE; case ICmpInst::ICMP_UGT: return Expression::ICMPUGT; @@ -243,7 +243,7 @@ Expression::ExpressionOpcode ValueTable::getOpcode(CmpInst* C) { } else { switch (C->getPredicate()) { default: // THIS SHOULD NEVER HAPPEN - LLVM_UNREACHABLE("Comparison with unknown predicate?"); + llvm_unreachable("Comparison with unknown predicate?"); case FCmpInst::FCMP_OEQ: return Expression::FCMPOEQ; case FCmpInst::FCMP_OGT: return Expression::FCMPOGT; case FCmpInst::FCMP_OGE: return Expression::FCMPOGE; @@ -265,7 +265,7 @@ Expression::ExpressionOpcode ValueTable::getOpcode(CmpInst* C) { Expression::ExpressionOpcode ValueTable::getOpcode(CastInst* C) { switch(C->getOpcode()) { default: // THIS SHOULD NEVER HAPPEN - LLVM_UNREACHABLE("Cast operator with unknown opcode?"); + llvm_unreachable("Cast operator with unknown opcode?"); case Instruction::Trunc: return Expression::TRUNC; case Instruction::ZExt: return Expression::ZEXT; case Instruction::SExt: return Expression::SEXT; diff --git a/lib/Transforms/Scalar/GVNPRE.cpp b/lib/Transforms/Scalar/GVNPRE.cpp index d5098f2..3f66131 100644 --- a/lib/Transforms/Scalar/GVNPRE.cpp +++ b/lib/Transforms/Scalar/GVNPRE.cpp @@ -241,7 +241,7 @@ Expression::ExpressionOpcode // THIS SHOULD NEVER HAPPEN default: - LLVM_UNREACHABLE("Binary operator with unknown opcode?"); + llvm_unreachable("Binary operator with unknown opcode?"); return Expression::ADD; } } @@ -272,7 +272,7 @@ Expression::ExpressionOpcode ValueTable::getOpcode(CmpInst* C) { // THIS SHOULD NEVER HAPPEN default: - LLVM_UNREACHABLE("Comparison with unknown predicate?"); + llvm_unreachable("Comparison with unknown predicate?"); return Expression::ICMPEQ; } } else { @@ -308,7 +308,7 @@ Expression::ExpressionOpcode ValueTable::getOpcode(CmpInst* C) { // THIS SHOULD NEVER HAPPEN default: - LLVM_UNREACHABLE("Comparison with unknown predicate?"); + llvm_unreachable("Comparison with unknown predicate?"); return Expression::FCMPOEQ; } } @@ -344,7 +344,7 @@ Expression::ExpressionOpcode // THIS SHOULD NEVER HAPPEN default: - LLVM_UNREACHABLE("Cast operator with unknown opcode?"); + llvm_unreachable("Cast operator with unknown opcode?"); return Expression::BITCAST; } } @@ -578,7 +578,7 @@ uint32_t ValueTable::lookup(Value* V) const { if (VI != valueNumbering.end()) return VI->second; else - LLVM_UNREACHABLE("Value not numbered?"); + llvm_unreachable("Value not numbered?"); return 0; } @@ -768,7 +768,7 @@ Value* GVNPRE::find_leader(ValueNumberedSet& vals, uint32_t v) { if (v == VN.lookup(*I)) return *I; - LLVM_UNREACHABLE("No leader found, but present bit is set?"); + llvm_unreachable("No leader found, but present bit is set?"); return 0; } diff --git a/lib/Transforms/Scalar/InstructionCombining.cpp b/lib/Transforms/Scalar/InstructionCombining.cpp index 864b2fa..f42827c 100644 --- a/lib/Transforms/Scalar/InstructionCombining.cpp +++ b/lib/Transforms/Scalar/InstructionCombining.cpp @@ -1682,7 +1682,7 @@ Value *InstCombiner::SimplifyDemandedVectorElts(Value *V, APInt DemandedElts, UndefElts = UndefElts2; if (VWidth > InVWidth) { - LLVM_UNREACHABLE("Unimp"); + llvm_unreachable("Unimp"); // If there are more elements in the result than there are in the source, // then an output element is undef if the corresponding input element is // undef. @@ -1690,7 +1690,7 @@ Value *InstCombiner::SimplifyDemandedVectorElts(Value *V, APInt DemandedElts, if (UndefElts2[OutIdx/Ratio]) UndefElts.set(OutIdx); } else if (VWidth < InVWidth) { - LLVM_UNREACHABLE("Unimp"); + llvm_unreachable("Unimp"); // If there are more elements in the source than there are in the result, // then a result element is undef if all of the corresponding input // elements are undef. @@ -1760,7 +1760,7 @@ Value *InstCombiner::SimplifyDemandedVectorElts(Value *V, APInt DemandedElts, RHS = InsertNewInstBefore(new ExtractElementInst(RHS, 0U,"tmp"), *II); switch (II->getIntrinsicID()) { - default: LLVM_UNREACHABLE("Case stmts out of sync!"); + default: llvm_unreachable("Case stmts out of sync!"); case Intrinsic::x86_sse_sub_ss: case Intrinsic::x86_sse2_sub_sd: TmpV = InsertNewInstBefore(BinaryOperator::CreateFSub(LHS, RHS, @@ -1931,7 +1931,7 @@ static Value *FoldOperationIntoSelectOperand(Instruction &I, Value *SO, New = CmpInst::Create(*Context, CI->getOpcode(), CI->getPredicate(), Op0, Op1, SO->getName()+".cmp"); else { - LLVM_UNREACHABLE("Unknown binary instruction type!"); + llvm_unreachable("Unknown binary instruction type!"); } return IC->InsertNewInstBefore(New, I); } @@ -2022,7 +2022,7 @@ Instruction *InstCombiner::FoldOpIntoPhi(Instruction &I) { PN->getIncomingValue(i), C, "phitmp", NonConstBB->getTerminator()); else - LLVM_UNREACHABLE("Unknown binop!"); + llvm_unreachable("Unknown binop!"); AddToWorkList(cast<Instruction>(InV)); } @@ -3367,7 +3367,7 @@ static unsigned getICmpCode(const ICmpInst *ICI) { case ICmpInst::ICMP_SLE: return 6; // 110 // True -> 7 default: - LLVM_UNREACHABLE("Invalid ICmp predicate!"); + llvm_unreachable("Invalid ICmp predicate!"); return 0; } } @@ -3395,7 +3395,7 @@ static unsigned getFCmpCode(FCmpInst::Predicate CC, bool &isOrdered) { // True -> 7 default: // Not expecting FCMP_FALSE and FCMP_TRUE; - LLVM_UNREACHABLE("Unexpected FCmp predicate!"); + llvm_unreachable("Unexpected FCmp predicate!"); return 0; } } @@ -3407,7 +3407,7 @@ static unsigned getFCmpCode(FCmpInst::Predicate CC, bool &isOrdered) { static Value *getICmpValue(bool sign, unsigned code, Value *LHS, Value *RHS, LLVMContext *Context) { switch (code) { - default: LLVM_UNREACHABLE("Illegal ICmp code!"); + default: llvm_unreachable("Illegal ICmp code!"); case 0: return Context->getConstantIntFalse(); case 1: if (sign) @@ -3441,7 +3441,7 @@ static Value *getICmpValue(bool sign, unsigned code, Value *LHS, Value *RHS, static Value *getFCmpValue(bool isordered, unsigned code, Value *LHS, Value *RHS, LLVMContext *Context) { switch (code) { - default: LLVM_UNREACHABLE("Illegal FCmp code!"); + default: llvm_unreachable("Illegal FCmp code!"); case 0: if (isordered) return new FCmpInst(*Context, FCmpInst::FCMP_ORD, LHS, RHS); @@ -3520,7 +3520,7 @@ struct FoldICmpLogical { case Instruction::And: Code = LHSCode & RHSCode; break; case Instruction::Or: Code = LHSCode | RHSCode; break; case Instruction::Xor: Code = LHSCode ^ RHSCode; break; - default: LLVM_UNREACHABLE("Illegal logical opcode!"); return 0; + default: llvm_unreachable("Illegal logical opcode!"); return 0; } bool isSigned = ICmpInst::isSignedPredicate(RHSICI->getPredicate()) || @@ -3855,10 +3855,10 @@ Instruction *InstCombiner::FoldAndOfICmps(Instruction &I, assert(LHSCst != RHSCst && "Compares not folded above?"); switch (LHSCC) { - default: LLVM_UNREACHABLE("Unknown integer condition code!"); + default: llvm_unreachable("Unknown integer condition code!"); case ICmpInst::ICMP_EQ: switch (RHSCC) { - default: LLVM_UNREACHABLE("Unknown integer condition code!"); + default: llvm_unreachable("Unknown integer condition code!"); case ICmpInst::ICMP_EQ: // (X == 13 & X == 15) -> false case ICmpInst::ICMP_UGT: // (X == 13 & X > 15) -> false case ICmpInst::ICMP_SGT: // (X == 13 & X > 15) -> false @@ -3870,7 +3870,7 @@ Instruction *InstCombiner::FoldAndOfICmps(Instruction &I, } case ICmpInst::ICMP_NE: switch (RHSCC) { - default: LLVM_UNREACHABLE("Unknown integer condition code!"); + default: llvm_unreachable("Unknown integer condition code!"); case ICmpInst::ICMP_ULT: if (LHSCst == SubOne(RHSCst, Context)) // (X != 13 & X u< 14) -> X < 13 return new ICmpInst(*Context, ICmpInst::ICMP_ULT, Val, LHSCst); @@ -3897,7 +3897,7 @@ Instruction *InstCombiner::FoldAndOfICmps(Instruction &I, break; case ICmpInst::ICMP_ULT: switch (RHSCC) { - default: LLVM_UNREACHABLE("Unknown integer condition code!"); + default: llvm_unreachable("Unknown integer condition code!"); case ICmpInst::ICMP_EQ: // (X u< 13 & X == 15) -> false case ICmpInst::ICMP_UGT: // (X u< 13 & X u> 15) -> false return ReplaceInstUsesWith(I, Context->getConstantIntFalse()); @@ -3912,7 +3912,7 @@ Instruction *InstCombiner::FoldAndOfICmps(Instruction &I, break; case ICmpInst::ICMP_SLT: switch (RHSCC) { - default: LLVM_UNREACHABLE("Unknown integer condition code!"); + default: llvm_unreachable("Unknown integer condition code!"); case ICmpInst::ICMP_EQ: // (X s< 13 & X == 15) -> false case ICmpInst::ICMP_SGT: // (X s< 13 & X s> 15) -> false return ReplaceInstUsesWith(I, Context->getConstantIntFalse()); @@ -3927,7 +3927,7 @@ Instruction *InstCombiner::FoldAndOfICmps(Instruction &I, break; case ICmpInst::ICMP_UGT: switch (RHSCC) { - default: LLVM_UNREACHABLE("Unknown integer condition code!"); + default: llvm_unreachable("Unknown integer condition code!"); case ICmpInst::ICMP_EQ: // (X u> 13 & X == 15) -> X == 15 case ICmpInst::ICMP_UGT: // (X u> 13 & X u> 15) -> X u> 15 return ReplaceInstUsesWith(I, RHS); @@ -3946,7 +3946,7 @@ Instruction *InstCombiner::FoldAndOfICmps(Instruction &I, break; case ICmpInst::ICMP_SGT: switch (RHSCC) { - default: LLVM_UNREACHABLE("Unknown integer condition code!"); + default: llvm_unreachable("Unknown integer condition code!"); case ICmpInst::ICMP_EQ: // (X s> 13 & X == 15) -> X == 15 case ICmpInst::ICMP_SGT: // (X s> 13 & X s> 15) -> X s> 15 return ReplaceInstUsesWith(I, RHS); @@ -4544,10 +4544,10 @@ Instruction *InstCombiner::FoldOrOfICmps(Instruction &I, assert(LHSCst != RHSCst && "Compares not folded above?"); switch (LHSCC) { - default: LLVM_UNREACHABLE("Unknown integer condition code!"); + default: llvm_unreachable("Unknown integer condition code!"); case ICmpInst::ICMP_EQ: switch (RHSCC) { - default: LLVM_UNREACHABLE("Unknown integer condition code!"); + default: llvm_unreachable("Unknown integer condition code!"); case ICmpInst::ICMP_EQ: if (LHSCst == SubOne(RHSCst, Context)) { // (X == 13 | X == 14) -> X-13 <u 2 @@ -4570,7 +4570,7 @@ Instruction *InstCombiner::FoldOrOfICmps(Instruction &I, break; case ICmpInst::ICMP_NE: switch (RHSCC) { - default: LLVM_UNREACHABLE("Unknown integer condition code!"); + default: llvm_unreachable("Unknown integer condition code!"); case ICmpInst::ICMP_EQ: // (X != 13 | X == 15) -> X != 13 case ICmpInst::ICMP_UGT: // (X != 13 | X u> 15) -> X != 13 case ICmpInst::ICMP_SGT: // (X != 13 | X s> 15) -> X != 13 @@ -4583,7 +4583,7 @@ Instruction *InstCombiner::FoldOrOfICmps(Instruction &I, break; case ICmpInst::ICMP_ULT: switch (RHSCC) { - default: LLVM_UNREACHABLE("Unknown integer condition code!"); + default: llvm_unreachable("Unknown integer condition code!"); case ICmpInst::ICMP_EQ: // (X u< 13 | X == 14) -> no change break; case ICmpInst::ICMP_UGT: // (X u< 13 | X u> 15) -> (X-13) u> 2 @@ -4604,7 +4604,7 @@ Instruction *InstCombiner::FoldOrOfICmps(Instruction &I, break; case ICmpInst::ICMP_SLT: switch (RHSCC) { - default: LLVM_UNREACHABLE("Unknown integer condition code!"); + default: llvm_unreachable("Unknown integer condition code!"); case ICmpInst::ICMP_EQ: // (X s< 13 | X == 14) -> no change break; case ICmpInst::ICMP_SGT: // (X s< 13 | X s> 15) -> (X-13) s> 2 @@ -4625,7 +4625,7 @@ Instruction *InstCombiner::FoldOrOfICmps(Instruction &I, break; case ICmpInst::ICMP_UGT: switch (RHSCC) { - default: LLVM_UNREACHABLE("Unknown integer condition code!"); + default: llvm_unreachable("Unknown integer condition code!"); case ICmpInst::ICMP_EQ: // (X u> 13 | X == 15) -> X u> 13 case ICmpInst::ICMP_UGT: // (X u> 13 | X u> 15) -> X u> 13 return ReplaceInstUsesWith(I, LHS); @@ -4640,7 +4640,7 @@ Instruction *InstCombiner::FoldOrOfICmps(Instruction &I, break; case ICmpInst::ICMP_SGT: switch (RHSCC) { - default: LLVM_UNREACHABLE("Unknown integer condition code!"); + default: llvm_unreachable("Unknown integer condition code!"); case ICmpInst::ICMP_EQ: // (X s> 13 | X == 15) -> X > 13 case ICmpInst::ICMP_SGT: // (X s> 13 | X s> 15) -> X > 13 return ReplaceInstUsesWith(I, LHS); @@ -5717,7 +5717,7 @@ Instruction *InstCombiner::FoldFCmp_IntToFP_Cst(FCmpInst &I, ICmpInst::Predicate Pred; switch (I.getPredicate()) { - default: LLVM_UNREACHABLE("Unexpected predicate!"); + default: llvm_unreachable("Unexpected predicate!"); case FCmpInst::FCMP_UEQ: case FCmpInst::FCMP_OEQ: Pred = ICmpInst::ICMP_EQ; @@ -5811,7 +5811,7 @@ Instruction *InstCombiner::FoldFCmp_IntToFP_Cst(FCmpInst &I, // the compare predicate and sometimes the value. RHSC is rounded towards // zero at this point. switch (Pred) { - default: LLVM_UNREACHABLE("Unexpected integer comparison!"); + default: llvm_unreachable("Unexpected integer comparison!"); case ICmpInst::ICMP_NE: // (float)int != 4.4 --> true return ReplaceInstUsesWith(I, Context->getConstantIntTrue()); case ICmpInst::ICMP_EQ: // (float)int == 4.4 --> false @@ -5888,7 +5888,7 @@ Instruction *InstCombiner::visitFCmpInst(FCmpInst &I) { // Simplify 'fcmp pred X, X' if (Op0 == Op1) { switch (I.getPredicate()) { - default: LLVM_UNREACHABLE("Unknown predicate!"); + default: llvm_unreachable("Unknown predicate!"); case FCmpInst::FCMP_UEQ: // True if unordered or equal case FCmpInst::FCMP_UGE: // True if unordered, greater than, or equal case FCmpInst::FCMP_ULE: // True if unordered, less than, or equal @@ -6007,7 +6007,7 @@ Instruction *InstCombiner::visitICmpInst(ICmpInst &I) { // icmp's with boolean values can always be turned into bitwise operations if (Ty == Type::Int1Ty) { switch (I.getPredicate()) { - default: LLVM_UNREACHABLE("Invalid icmp instruction!"); + default: llvm_unreachable("Invalid icmp instruction!"); case ICmpInst::ICMP_EQ: { // icmp eq i1 A, B -> ~(A^B) Instruction *Xor = BinaryOperator::CreateXor(Op0, Op1, I.getName()+"tmp"); InsertNewInstBefore(Xor, I); @@ -6153,7 +6153,7 @@ Instruction *InstCombiner::visitICmpInst(ICmpInst &I) { // Based on the range information we know about the LHS, see if we can // simplify this comparison. For example, (x&4) < 8 is always true. switch (I.getPredicate()) { - default: LLVM_UNREACHABLE("Unknown icmp opcode!"); + default: llvm_unreachable("Unknown icmp opcode!"); case ICmpInst::ICMP_EQ: if (Op0Max.ult(Op1Min) || Op0Min.ugt(Op1Max)) return ReplaceInstUsesWith(I, Context->getConstantIntFalse()); @@ -6662,7 +6662,7 @@ Instruction *InstCombiner::FoldICmpDivCst(ICmpInst &ICI, BinaryOperator *DivI, Value *X = DivI->getOperand(0); switch (Pred) { - default: LLVM_UNREACHABLE("Unhandled icmp opcode!"); + default: llvm_unreachable("Unhandled icmp opcode!"); case ICmpInst::ICMP_EQ: if (LoOverflow && HiOverflow) return ReplaceInstUsesWith(ICI, Context->getConstantIntFalse()); @@ -8117,7 +8117,7 @@ Value *InstCombiner::EvaluateInDifferentType(Value *V, const Type *Ty, } default: // TODO: Can handle more cases here. - LLVM_UNREACHABLE("Unreachable!"); + llvm_unreachable("Unreachable!"); break; } @@ -8329,7 +8329,7 @@ Instruction *InstCombiner::commonIntCastTransforms(CastInst &CI) { default: // All the others use floating point so we shouldn't actually // get here because of the check above. - LLVM_UNREACHABLE("Unknown cast type"); + llvm_unreachable("Unknown cast type"); case Instruction::Trunc: DoXForm = true; break; @@ -8385,7 +8385,7 @@ Instruction *InstCombiner::commonIntCastTransforms(CastInst &CI) { assert(Res->getType() == DestTy); switch (CI.getOpcode()) { - default: LLVM_UNREACHABLE("Unknown cast type!"); + default: llvm_unreachable("Unknown cast type!"); case Instruction::Trunc: // Just replace this cast with the result. return ReplaceInstUsesWith(CI, Res); @@ -9102,7 +9102,7 @@ static unsigned GetSelectFoldableOperands(Instruction *I) { static Constant *GetSelectFoldableConstant(Instruction *I, LLVMContext *Context) { switch (I->getOpcode()) { - default: LLVM_UNREACHABLE("This cannot happen!"); + default: llvm_unreachable("This cannot happen!"); case Instruction::Add: case Instruction::Sub: case Instruction::Or: @@ -9184,7 +9184,7 @@ Instruction *InstCombiner::FoldSelectOpOp(SelectInst &SI, Instruction *TI, else return BinaryOperator::Create(BO->getOpcode(), NewSI, MatchOp); } - LLVM_UNREACHABLE("Shouldn't get here"); + llvm_unreachable("Shouldn't get here"); return 0; } @@ -9226,7 +9226,7 @@ Instruction *InstCombiner::FoldSelectIntoOp(SelectInst &SI, Value *TrueVal, NewSel->takeName(TVI); if (BinaryOperator *BO = dyn_cast<BinaryOperator>(TVI)) return BinaryOperator::Create(BO->getOpcode(), FalseVal, NewSel); - LLVM_UNREACHABLE("Unknown instruction!!"); + llvm_unreachable("Unknown instruction!!"); } } } @@ -9255,7 +9255,7 @@ Instruction *InstCombiner::FoldSelectIntoOp(SelectInst &SI, Value *TrueVal, NewSel->takeName(FVI); if (BinaryOperator *BO = dyn_cast<BinaryOperator>(FVI)) return BinaryOperator::Create(BO->getOpcode(), TrueVal, NewSel); - LLVM_UNREACHABLE("Unknown instruction!!"); + llvm_unreachable("Unknown instruction!!"); } } } diff --git a/lib/Transforms/Scalar/SCCP.cpp b/lib/Transforms/Scalar/SCCP.cpp index 830895c..6ada288 100644 --- a/lib/Transforms/Scalar/SCCP.cpp +++ b/lib/Transforms/Scalar/SCCP.cpp @@ -456,7 +456,7 @@ void SCCPSolver::getFeasibleSuccessors(TerminatorInst &TI, } else if (SCValue.isConstant()) Succs[SI->findCaseValue(cast<ConstantInt>(SCValue.getConstant()))] = true; } else { - LLVM_UNREACHABLE("SCCP: Don't know how to handle this terminator!"); + llvm_unreachable("SCCP: Don't know how to handle this terminator!"); } } @@ -517,7 +517,7 @@ bool SCCPSolver::isEdgeFeasible(BasicBlock *From, BasicBlock *To) { #ifndef NDEBUG cerr << "Unknown terminator instruction: " << *TI; #endif - llvm_unreachable(); + llvm_unreachable(0); } } @@ -1806,7 +1806,7 @@ bool IPSCCP::runOnModule(Module &M) { } else if (SwitchInst *SI = dyn_cast<SwitchInst>(I)) { assert(isa<UndefValue>(SI->getCondition()) && "Switch should fold"); } else { - LLVM_UNREACHABLE("Didn't fold away reference to block!"); + llvm_unreachable("Didn't fold away reference to block!"); } #endif diff --git a/lib/Transforms/Scalar/ScalarReplAggregates.cpp b/lib/Transforms/Scalar/ScalarReplAggregates.cpp index 2c97e57..83db90d 100644 --- a/lib/Transforms/Scalar/ScalarReplAggregates.cpp +++ b/lib/Transforms/Scalar/ScalarReplAggregates.cpp @@ -267,7 +267,7 @@ bool SROA::performScalarRepl(Function &F) { // Check that all of the users of the allocation are capable of being // transformed. switch (isSafeAllocaToScalarRepl(AI)) { - default: LLVM_UNREACHABLE("Unexpected value!"); + default: llvm_unreachable("Unexpected value!"); case 0: // Not safe to scalar replace. break; case 1: // Safe, but requires cleanup/canonicalizations first @@ -1511,7 +1511,7 @@ void SROA::ConvertUsesToScalar(Value *Ptr, AllocaInst *NewAI, uint64_t Offset) { continue; } - LLVM_UNREACHABLE("Unsupported operation!"); + llvm_unreachable("Unsupported operation!"); } } diff --git a/lib/Transforms/Utils/BasicBlockUtils.cpp b/lib/Transforms/Utils/BasicBlockUtils.cpp index c9af474..b8663de 100644 --- a/lib/Transforms/Utils/BasicBlockUtils.cpp +++ b/lib/Transforms/Utils/BasicBlockUtils.cpp @@ -264,7 +264,7 @@ void llvm::RemoveSuccessor(TerminatorInst *TI, unsigned SuccNum) { case Instruction::Switch: // Should remove entry default: case Instruction::Ret: // Cannot happen, has no successors! - LLVM_UNREACHABLE("Unhandled terminator instruction type in RemoveSuccessor!"); + llvm_unreachable("Unhandled terminator instruction type in RemoveSuccessor!"); } if (NewTI) // If it's a different instruction, replace. diff --git a/lib/Transforms/Utils/BreakCriticalEdges.cpp b/lib/Transforms/Utils/BreakCriticalEdges.cpp index f45f24c..bef1119 100644 --- a/lib/Transforms/Utils/BreakCriticalEdges.cpp +++ b/lib/Transforms/Utils/BreakCriticalEdges.cpp @@ -223,7 +223,7 @@ bool llvm::SplitCriticalEdge(TerminatorInst *TI, unsigned SuccNum, Pass *P, // If NewBBDominatesDestBB hasn't been computed yet, do so with DF. if (!OtherPreds.empty()) { // FIXME: IMPLEMENT THIS! - LLVM_UNREACHABLE("Requiring domfrontiers but not idom/domtree/domset." + llvm_unreachable("Requiring domfrontiers but not idom/domtree/domset." " not implemented yet!"); } diff --git a/lib/Transforms/Utils/ValueMapper.cpp b/lib/Transforms/Utils/ValueMapper.cpp index 951d24f..f0b24c1 100644 --- a/lib/Transforms/Utils/ValueMapper.cpp +++ b/lib/Transforms/Utils/ValueMapper.cpp @@ -127,7 +127,7 @@ Value *llvm::MapValue(const Value *V, ValueMapTy &VM, LLVMContext *Context) { return VM[V] = C; } else { - LLVM_UNREACHABLE("Unknown type of constant!"); + llvm_unreachable("Unknown type of constant!"); } } diff --git a/lib/VMCore/AsmWriter.cpp b/lib/VMCore/AsmWriter.cpp index a49c09a..eab845f 100644 --- a/lib/VMCore/AsmWriter.cpp +++ b/lib/VMCore/AsmWriter.cpp @@ -97,7 +97,7 @@ static void PrintLLVMName(raw_ostream &OS, const char *NameStr, unsigned NameLen, PrefixType Prefix) { assert(NameStr && "Cannot get empty name!"); switch (Prefix) { - default: LLVM_UNREACHABLE("Bad prefix!"); + default: llvm_unreachable("Bad prefix!"); case NoPrefix: break; case GlobalPrefix: OS << '@'; break; case LabelPrefix: break; @@ -937,7 +937,7 @@ static void WriteConstantInt(raw_ostream &Out, const Constant *CV, else if (&CFP->getValueAPF().getSemantics() == &APFloat::PPCDoubleDouble) Out << 'M'; else - LLVM_UNREACHABLE("Unsupported floating point type"); + llvm_unreachable("Unsupported floating point type"); // api needed to prevent premature destruction APInt api = CFP->getValueAPF().bitcastToAPInt(); const uint64_t* p = api.getRawData(); @@ -1210,7 +1210,7 @@ public: else if (const Function *F = dyn_cast<Function>(G)) printFunction(F); else - LLVM_UNREACHABLE("Unknown global"); + llvm_unreachable("Unknown global"); } void write(const BasicBlock *BB) { printBasicBlock(BB); } @@ -1350,7 +1350,7 @@ static void PrintLinkage(GlobalValue::LinkageTypes LT, raw_ostream &Out) { case GlobalValue::ExternalWeakLinkage: Out << "extern_weak "; break; case GlobalValue::ExternalLinkage: break; case GlobalValue::GhostLinkage: - LLVM_UNREACHABLE("GhostLinkage not allowed in AsmWriter!"); + llvm_unreachable("GhostLinkage not allowed in AsmWriter!"); } } @@ -1358,7 +1358,7 @@ static void PrintLinkage(GlobalValue::LinkageTypes LT, raw_ostream &Out) { static void PrintVisibility(GlobalValue::VisibilityTypes Vis, raw_ostream &Out) { switch (Vis) { - default: LLVM_UNREACHABLE("Invalid visibility style!"); + default: llvm_unreachable("Invalid visibility style!"); case GlobalValue::DefaultVisibility: break; case GlobalValue::HiddenVisibility: Out << "hidden "; break; case GlobalValue::ProtectedVisibility: Out << "protected "; break; @@ -1970,7 +1970,7 @@ void Value::print(raw_ostream &OS, AssemblyAnnotationWriter *AAW) const { } else if (isa<InlineAsm>(this)) { WriteAsOperand(OS, this, true, 0); } else { - LLVM_UNREACHABLE("Unknown value to print out!"); + llvm_unreachable("Unknown value to print out!"); } } diff --git a/lib/VMCore/AutoUpgrade.cpp b/lib/VMCore/AutoUpgrade.cpp index f3aa742..c3405fc 100644 --- a/lib/VMCore/AutoUpgrade.cpp +++ b/lib/VMCore/AutoUpgrade.cpp @@ -334,13 +334,13 @@ void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) { // Clean up the old call now that it has been completely upgraded. CI->eraseFromParent(); } else { - LLVM_UNREACHABLE("Unknown function for CallInst upgrade."); + llvm_unreachable("Unknown function for CallInst upgrade."); } return; } switch (NewFn->getIntrinsicID()) { - default: LLVM_UNREACHABLE("Unknown function for CallInst upgrade."); + default: llvm_unreachable("Unknown function for CallInst upgrade."); case Intrinsic::x86_mmx_psll_d: case Intrinsic::x86_mmx_psll_q: case Intrinsic::x86_mmx_psll_w: diff --git a/lib/VMCore/ConstantFold.cpp b/lib/VMCore/ConstantFold.cpp index 4a5c224..7b10f44 100644 --- a/lib/VMCore/ConstantFold.cpp +++ b/lib/VMCore/ConstantFold.cpp @@ -313,7 +313,7 @@ Constant *llvm::ConstantFoldCastInstruction(LLVMContext &Context, break; } - LLVM_UNREACHABLE("Failed to cast constant expression"); + llvm_unreachable("Failed to cast constant expression"); return 0; } @@ -1418,7 +1418,7 @@ Constant *llvm::ConstantFoldCompareInstruction(LLVMContext &Context, APInt V1 = cast<ConstantInt>(C1)->getValue(); APInt V2 = cast<ConstantInt>(C2)->getValue(); switch (pred) { - default: LLVM_UNREACHABLE("Invalid ICmp Predicate"); return 0; + default: llvm_unreachable("Invalid ICmp Predicate"); return 0; case ICmpInst::ICMP_EQ: return Context.getConstantInt(Type::Int1Ty, V1 == V2); case ICmpInst::ICMP_NE: @@ -1445,7 +1445,7 @@ Constant *llvm::ConstantFoldCompareInstruction(LLVMContext &Context, APFloat C2V = cast<ConstantFP>(C2)->getValueAPF(); APFloat::cmpResult R = C1V.compare(C2V); switch (pred) { - default: LLVM_UNREACHABLE("Invalid FCmp Predicate"); return 0; + default: llvm_unreachable("Invalid FCmp Predicate"); return 0; case FCmpInst::FCMP_FALSE: return Context.getConstantIntFalse(); case FCmpInst::FCMP_TRUE: return Context.getConstantIntTrue(); case FCmpInst::FCMP_UNO: @@ -1502,7 +1502,7 @@ Constant *llvm::ConstantFoldCompareInstruction(LLVMContext &Context, if (C1->getType()->isFloatingPoint()) { int Result = -1; // -1 = unknown, 0 = known false, 1 = known true. switch (evaluateFCmpRelation(Context, C1, C2)) { - default: LLVM_UNREACHABLE("Unknown relation!"); + default: llvm_unreachable("Unknown relation!"); case FCmpInst::FCMP_UNO: case FCmpInst::FCMP_ORD: case FCmpInst::FCMP_UEQ: @@ -1561,7 +1561,7 @@ Constant *llvm::ConstantFoldCompareInstruction(LLVMContext &Context, // Evaluate the relation between the two constants, per the predicate. int Result = -1; // -1 = unknown, 0 = known false, 1 = known true. switch (evaluateICmpRelation(Context, C1, C2, CmpInst::isSigned(pred))) { - default: LLVM_UNREACHABLE("Unknown relational!"); + default: llvm_unreachable("Unknown relational!"); case ICmpInst::BAD_ICMP_PREDICATE: break; // Couldn't determine anything about these constants. case ICmpInst::ICMP_EQ: // We know the constants are equal! diff --git a/lib/VMCore/Constants.cpp b/lib/VMCore/Constants.cpp index 390cb7b..33c8f67 100644 --- a/lib/VMCore/Constants.cpp +++ b/lib/VMCore/Constants.cpp @@ -964,7 +964,7 @@ namespace llvm { template<class ConstantClass, class TypeClass> struct VISIBILITY_HIDDEN ConvertConstantType { static void convert(ConstantClass *OldC, const TypeClass *NewTy) { - LLVM_UNREACHABLE("This type cannot be converted!"); + llvm_unreachable("This type cannot be converted!"); } }; @@ -1782,7 +1782,7 @@ namespace llvm { if (V.opcode == Instruction::FCmp) return new CompareConstantExpr(Ty, Instruction::FCmp, V.predicate, V.operands[0], V.operands[1]); - LLVM_UNREACHABLE("Invalid ConstantExpr!"); + llvm_unreachable("Invalid ConstantExpr!"); return 0; } }; @@ -1874,7 +1874,7 @@ Constant *ConstantExpr::getCast(unsigned oc, Constant *C, const Type *Ty) { switch (opc) { default: - LLVM_UNREACHABLE("Invalid cast opcode"); + llvm_unreachable("Invalid cast opcode"); break; case Instruction::Trunc: return getTrunc(C, Ty); case Instruction::ZExt: return getZExt(C, Ty); @@ -2113,7 +2113,7 @@ Constant *ConstantExpr::getTy(const Type *ReqTy, unsigned Opcode, Constant *ConstantExpr::getCompareTy(unsigned short predicate, Constant *C1, Constant *C2) { switch (predicate) { - default: LLVM_UNREACHABLE("Invalid CmpInst predicate"); + default: llvm_unreachable("Invalid CmpInst predicate"); case CmpInst::FCMP_FALSE: case CmpInst::FCMP_OEQ: case CmpInst::FCMP_OGT: case CmpInst::FCMP_OGE: case CmpInst::FCMP_OLT: case CmpInst::FCMP_OLE: case CmpInst::FCMP_ONE: case CmpInst::FCMP_ORD: case CmpInst::FCMP_UNO: @@ -2715,7 +2715,7 @@ void ConstantExpr::replaceUsesOfWithOnConstant(Value *From, Value *ToV, if (C2 == From) C2 = To; Replacement = ConstantExpr::get(getOpcode(), C1, C2); } else { - LLVM_UNREACHABLE("Unknown ConstantExpr type!"); + llvm_unreachable("Unknown ConstantExpr type!"); return; } diff --git a/lib/VMCore/Core.cpp b/lib/VMCore/Core.cpp index 068735e..d04701e 100644 --- a/lib/VMCore/Core.cpp +++ b/lib/VMCore/Core.cpp @@ -1063,7 +1063,7 @@ unsigned LLVMGetInstructionCallConv(LLVMValueRef Instr) { return CI->getCallingConv(); else if (InvokeInst *II = dyn_cast<InvokeInst>(V)) return II->getCallingConv(); - LLVM_UNREACHABLE("LLVMGetInstructionCallConv applies only to call and invoke!"); + llvm_unreachable("LLVMGetInstructionCallConv applies only to call and invoke!"); return 0; } @@ -1073,7 +1073,7 @@ void LLVMSetInstructionCallConv(LLVMValueRef Instr, unsigned CC) { return CI->setCallingConv(CC); else if (InvokeInst *II = dyn_cast<InvokeInst>(V)) return II->setCallingConv(CC); - LLVM_UNREACHABLE("LLVMSetInstructionCallConv applies only to call and invoke!"); + llvm_unreachable("LLVMSetInstructionCallConv applies only to call and invoke!"); } void LLVMAddInstrAttribute(LLVMValueRef Instr, unsigned index, diff --git a/lib/VMCore/Globals.cpp b/lib/VMCore/Globals.cpp index adc7a82..5c05308 100644 --- a/lib/VMCore/Globals.cpp +++ b/lib/VMCore/Globals.cpp @@ -79,7 +79,7 @@ void GlobalValue::removeDeadConstantUsers() const { /// Override destroyConstant to make sure it doesn't get called on /// GlobalValue's because they shouldn't be treated like other constants. void GlobalValue::destroyConstant() { - LLVM_UNREACHABLE("You can't GV->destroyConstant()!"); + llvm_unreachable("You can't GV->destroyConstant()!"); } /// copyAttributesFrom - copy all additional attributes (those not needed to @@ -246,7 +246,7 @@ const GlobalValue *GlobalAlias::getAliasedGlobal() const { CE->getOpcode() == Instruction::GetElementPtr)) return dyn_cast<GlobalValue>(CE->getOperand(0)); else - LLVM_UNREACHABLE("Unsupported aliasee"); + llvm_unreachable("Unsupported aliasee"); } } return 0; diff --git a/lib/VMCore/Instructions.cpp b/lib/VMCore/Instructions.cpp index 9a49bfc..8ce40a9 100644 --- a/lib/VMCore/Instructions.cpp +++ b/lib/VMCore/Instructions.cpp @@ -536,11 +536,11 @@ unsigned ReturnInst::getNumSuccessorsV() const { /// Out-of-line ReturnInst method, put here so the C++ compiler can choose to /// emit the vtable for the class in this translation unit. void ReturnInst::setSuccessorV(unsigned idx, BasicBlock *NewSucc) { - LLVM_UNREACHABLE("ReturnInst has no successors!"); + llvm_unreachable("ReturnInst has no successors!"); } BasicBlock *ReturnInst::getSuccessorV(unsigned idx) const { - LLVM_UNREACHABLE("ReturnInst has no successors!"); + llvm_unreachable("ReturnInst has no successors!"); return 0; } @@ -564,11 +564,11 @@ unsigned UnwindInst::getNumSuccessorsV() const { } void UnwindInst::setSuccessorV(unsigned idx, BasicBlock *NewSucc) { - LLVM_UNREACHABLE("UnwindInst has no successors!"); + llvm_unreachable("UnwindInst has no successors!"); } BasicBlock *UnwindInst::getSuccessorV(unsigned idx) const { - LLVM_UNREACHABLE("UnwindInst has no successors!"); + llvm_unreachable("UnwindInst has no successors!"); return 0; } @@ -588,11 +588,11 @@ unsigned UnreachableInst::getNumSuccessorsV() const { } void UnreachableInst::setSuccessorV(unsigned idx, BasicBlock *NewSucc) { - LLVM_UNREACHABLE("UnwindInst has no successors!"); + llvm_unreachable("UnwindInst has no successors!"); } BasicBlock *UnreachableInst::getSuccessorV(unsigned idx) const { - LLVM_UNREACHABLE("UnwindInst has no successors!"); + llvm_unreachable("UnwindInst has no successors!"); return 0; } @@ -2298,7 +2298,7 @@ CastInst::getCastOpcode( PTy = NULL; return BitCast; // same size, no-op cast } else { - LLVM_UNREACHABLE("Casting pointer or non-first class to float"); + llvm_unreachable("Casting pointer or non-first class to float"); } } else if (const VectorType *DestPTy = dyn_cast<VectorType>(DestTy)) { if (const VectorType *SrcPTy = dyn_cast<VectorType>(SrcTy)) { @@ -2709,7 +2709,7 @@ ICmpInst::makeConstantRange(Predicate pred, const APInt &C) { APInt Upper(C); uint32_t BitWidth = C.getBitWidth(); switch (pred) { - default: LLVM_UNREACHABLE("Invalid ICmp opcode to ConstantRange ctor!"); + default: llvm_unreachable("Invalid ICmp opcode to ConstantRange ctor!"); case ICmpInst::ICMP_EQ: Upper++; break; case ICmpInst::ICMP_NE: Lower++; break; case ICmpInst::ICMP_ULT: Lower = APInt::getMinValue(BitWidth); break; diff --git a/lib/VMCore/PassManager.cpp b/lib/VMCore/PassManager.cpp index a454b56..659120b 100644 --- a/lib/VMCore/PassManager.cpp +++ b/lib/VMCore/PassManager.cpp @@ -724,7 +724,7 @@ void PMDataManager::verifyDomInfo(Pass &P, Function &F) { OtherDT.dump(); cerr << "----- Invalid -----\n"; DT->dump(); - LLVM_UNREACHABLE("Invalid dominator info"); + llvm_unreachable("Invalid dominator info"); } DominanceFrontier *DF = P.getAnalysisIfAvailable<DominanceFrontier>(); @@ -741,7 +741,7 @@ void PMDataManager::verifyDomInfo(Pass &P, Function &F) { OtherDF.dump(); cerr << "----- Invalid -----\n"; DF->dump(); - LLVM_UNREACHABLE("Invalid dominator info"); + llvm_unreachable("Invalid dominator info"); } } @@ -883,7 +883,7 @@ void PMDataManager::add(Pass *P, bool ProcessAnalysis) { // Keep track of higher level analysis used by this manager. HigherLevelAnalysis.push_back(PRequired); } else - LLVM_UNREACHABLE("Unable to accomodate Required Pass"); + llvm_unreachable("Unable to accomodate Required Pass"); } // Set P as P's last user until someone starts using P. @@ -1106,7 +1106,7 @@ void PMDataManager::addLowerLevelRequiredPass(Pass *P, Pass *RequiredPass) { cerr << "Unable to schedule '" << RequiredPass->getPassName(); cerr << "' required by '" << P->getPassName() << "'\n"; #endif - LLVM_UNREACHABLE("Unable to schedule pass"); + llvm_unreachable("Unable to schedule pass"); } // Destructor diff --git a/lib/VMCore/Type.cpp b/lib/VMCore/Type.cpp index c94e911..9ceed26 100644 --- a/lib/VMCore/Type.cpp +++ b/lib/VMCore/Type.cpp @@ -265,10 +265,10 @@ const Type *Type::getForwardedTypeInternal() const { } void Type::refineAbstractType(const DerivedType *OldTy, const Type *NewTy) { - LLVM_UNREACHABLE("Attempting to refine a derived type!"); + llvm_unreachable("Attempting to refine a derived type!"); } void Type::typeBecameConcrete(const DerivedType *AbsTy) { - LLVM_UNREACHABLE("DerivedType is already a concrete type!"); + llvm_unreachable("DerivedType is already a concrete type!"); } @@ -634,7 +634,7 @@ static bool TypesEqual(const Type *Ty, const Type *Ty2, } return true; } else { - LLVM_UNREACHABLE("Unknown derived type!"); + llvm_unreachable("Unknown derived type!"); return false; } } diff --git a/lib/VMCore/Value.cpp b/lib/VMCore/Value.cpp index 94bafdf..f3d561f 100644 --- a/lib/VMCore/Value.cpp +++ b/lib/VMCore/Value.cpp @@ -516,7 +516,7 @@ void ValueHandleBase::ValueIsDeleted(Value *V) { cerr << "While deleting: " << *V->getType() << " %" << V->getNameStr() << "\n"; #endif - LLVM_UNREACHABLE("An asserting value handle still pointed to this" + llvm_unreachable("An asserting value handle still pointed to this" " value!"); case Weak: // Weak just goes to null, which will unlink it from the list. diff --git a/lib/VMCore/ValueTypes.cpp b/lib/VMCore/ValueTypes.cpp index 82b030e..6e2917b 100644 --- a/lib/VMCore/ValueTypes.cpp +++ b/lib/VMCore/ValueTypes.cpp @@ -91,7 +91,7 @@ std::string MVT::getMVTString() const { getVectorElementType().getMVTString(); if (isInteger()) return "i" + utostr(getSizeInBits()); - LLVM_UNREACHABLE("Invalid MVT!"); + llvm_unreachable("Invalid MVT!"); return "?"; case MVT::i1: return "i1"; case MVT::i8: return "i8"; @@ -184,7 +184,7 @@ MVT MVT::getMVT(const Type *Ty, bool HandleUnknown){ switch (Ty->getTypeID()) { default: if (HandleUnknown) return MVT::Other; - LLVM_UNREACHABLE("Unknown type!"); + llvm_unreachable("Unknown type!"); return MVT::isVoid; case Type::VoidTyID: return MVT::isVoid; diff --git a/lib/VMCore/Verifier.cpp b/lib/VMCore/Verifier.cpp index 1f43569..897e62c 100644 --- a/lib/VMCore/Verifier.cpp +++ b/lib/VMCore/Verifier.cpp @@ -208,7 +208,7 @@ namespace { if (!Broken) return false; msgs << "Broken module found, "; switch (action) { - default: LLVM_UNREACHABLE("Unknown action"); + default: llvm_unreachable("Unknown action"); case AbortProcessAction: msgs << "compilation aborted!\n"; cerr << msgs.str(); @@ -1117,7 +1117,7 @@ void Verifier::visitBinaryOperator(BinaryOperator &B) { "Shift return type must be same as operands!", &B); break; default: - LLVM_UNREACHABLE("Unknown BinaryOperator opcode!"); + llvm_unreachable("Unknown BinaryOperator opcode!"); } visitInstruction(B); |