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author | Chris Lattner <sabre@nondot.org> | 2006-06-08 18:03:49 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2006-06-08 18:03:49 +0000 |
commit | c0bad5706eff2dec7304b9266657ffdded0628d9 (patch) | |
tree | 25f04600f596d61d01a3a873ebf1207a499552b8 /lib | |
parent | fd561cded3cbaec1a4bdfae0703b4be4ea4092f3 (diff) | |
download | external_llvm-c0bad5706eff2dec7304b9266657ffdded0628d9.zip external_llvm-c0bad5706eff2dec7304b9266657ffdded0628d9.tar.gz external_llvm-c0bad5706eff2dec7304b9266657ffdded0628d9.tar.bz2 |
Add support for "m" inline asm constraints.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28728 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/Target/X86/X86ISelDAGToDAG.cpp | 30 |
1 files changed, 29 insertions, 1 deletions
diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp index 7f7e069..a1512be 100644 --- a/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -128,7 +128,13 @@ namespace { bool TryFoldLoad(SDOperand P, SDOperand N, SDOperand &Base, SDOperand &Scale, SDOperand &Index, SDOperand &Disp); - + /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for + /// inline asm expressions. + virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op, + char ConstraintCode, + std::vector<SDOperand> &OutOps, + SelectionDAG &DAG); + void EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI); inline void getAddressOperands(X86ISelAddressMode &AM, SDOperand &Base, @@ -876,6 +882,28 @@ void X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) { #endif } +bool X86DAGToDAGISel:: +SelectInlineAsmMemoryOperand(const SDOperand &Op, char ConstraintCode, + std::vector<SDOperand> &OutOps, SelectionDAG &DAG){ + SDOperand Op0, Op1, Op2, Op3; + switch (ConstraintCode) { + case 'o': // offsetable ?? + case 'v': // not offsetable ?? + default: return true; + case 'm': // memory + if (!SelectAddr(Op, Op0, Op1, Op2, Op3)) + return true; + break; + } + + OutOps.resize(4); + Select(OutOps[0], Op0); + Select(OutOps[1], Op1); + Select(OutOps[2], Op2); + Select(OutOps[3], Op3); + return false; +} + /// createX86ISelDag - This pass converts a legalized DAG into a /// X86-specific DAG, ready for instruction scheduling. /// |