Move XForm instructions over to the auto-generated asm writer

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15962 91177308-0d34-0410-b5e6-96231b3b80d8

4 files changed, 139 insertions, 71 deletions

diff --git a/lib/Target/PowerPC/PPC32AsmPrinter.cpp b/lib/Target/PowerPC/PPC32AsmPrinter.cpp
index 1d31e3b..03fc210 100644
--- a/lib/Target/PowerPC/PPC32AsmPrinter.cpp
+++ b/lib/Target/PowerPC/PPC32AsmPrinter.cpp
@@ -86,6 +86,12 @@ namespace {
       }
     }
 
+    void printU5ImmOperand(const MachineInstr *MI, unsigned OpNo,
+                            MVT::ValueType VT) {
+      unsigned char value = MI->getOperand(OpNo).getImmedValue();
+      assert(0 <= value && 31 >= value && "Invalid u5imm argument!");
+      O << (unsigned int)value;
+    }
     void printU16ImmOperand(const MachineInstr *MI, unsigned OpNo,
                             MVT::ValueType VT) {
       O << (unsigned short)MI->getOperand(OpNo).getImmedValue();
diff --git a/lib/Target/PowerPC/PPCAsmPrinter.cpp b/lib/Target/PowerPC/PPCAsmPrinter.cpp
index 1d31e3b..03fc210 100644
--- a/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ b/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -86,6 +86,12 @@ namespace {
       }
     }
 
+    void printU5ImmOperand(const MachineInstr *MI, unsigned OpNo,
+                            MVT::ValueType VT) {
+      unsigned char value = MI->getOperand(OpNo).getImmedValue();
+      assert(0 <= value && 31 >= value && "Invalid u5imm argument!");
+      O << (unsigned int)value;
+    }
     void printU16ImmOperand(const MachineInstr *MI, unsigned OpNo,
                             MVT::ValueType VT) {
       O << (unsigned short)MI->getOperand(OpNo).getImmedValue();
diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td
index c0930e7..4af8437 100644
--- a/lib/Target/PowerPC/PPCInstrFormats.td
+++ b/lib/Target/PowerPC/PPCInstrFormats.td
@@ -252,8 +252,8 @@ class DSForm_2<string name, bits<6> opcode, bits<2> xo, bit ppc64, bit vmx>
   : DSForm_1<name, opcode, xo, ppc64, vmx>;
 
 // 1.7.6 X-Form
-class XForm_base_r3xo<string name, bits<6> opcode, bits<10> xo, bit rc, 
-                      bit ppc64, bit vmx> : I<name, opcode, ppc64, vmx> {
+class XForm_base_r3xo<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
+                      dag OL, string asmstr> : I<"", opcode, ppc64, vmx> {
   field bits<5> RST;
   field bits<5> A;
   field bits<5> B;
@@ -270,14 +270,18 @@ class XForm_base_r3xo<string name, bits<6> opcode, bits<10> xo, bit rc,
   let Inst{16-20} = B;
   let Inst{21-30} = xo;
   let Inst{31}    = rc;
+  let OperandList = OL;
+  let AsmString = asmstr;
 }
 
 
-class XForm_1<string name, bits<6> opcode, bits<10> xo, bit ppc64, 
-              bit vmx> : XForm_base_r3xo<name, opcode, xo, 0, ppc64, vmx>;
+class XForm_1<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
+              dag OL, string asmstr> 
+  : XForm_base_r3xo<opcode, xo, 0, ppc64, vmx, OL, asmstr>;
 
-class XForm_5<string name, bits<6> opcode, bits<10> xo, bit ppc64, 
-              bit vmx> : XForm_base_r3xo<name, opcode, xo, 0, ppc64, vmx> {
+class XForm_5<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
+              dag OL, string asmstr>
+  : XForm_base_r3xo<opcode, xo, 0, ppc64, vmx, OL, asmstr> {
   let ArgCount = 1;
   let Arg1Type = 0;
   let Arg2Type = 0;
@@ -285,22 +289,23 @@ class XForm_5<string name, bits<6> opcode, bits<10> xo, bit ppc64,
   let B = 0;
 }
 
-class XForm_6<string name, bits<6> opcode, bits<10> xo, bit rc, bit ppc64, 
-              bit vmx> : XForm_base_r3xo<name, opcode, xo, rc, ppc64, vmx>;
-
-class XForm_7<string name, bits<6> opcode, bits<10> xo, bit ppc64, bit vmx> 
-  : XForm_base_r3xo<name, opcode, xo, 1, ppc64, vmx>;
+class XForm_6<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
+              dag OL, string asmstr> 
+  : XForm_base_r3xo<opcode, xo, rc, ppc64, vmx, OL, asmstr>;
 
-class XForm_8<string name, bits<6> opcode, bits<10> xo, bit ppc64, bit vmx>
-  : XForm_base_r3xo<name, opcode, xo, 0, ppc64, vmx>;
+class XForm_8<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
+              dag OL, string asmstr> 
+  : XForm_base_r3xo<opcode, xo, 0, ppc64, vmx, OL, asmstr>;
 
-class XForm_10<string name, bits<6> opcode, bits<10> xo, bit rc, bit ppc64, 
-               bit vmx> : XForm_base_r3xo<name, opcode, xo, rc, ppc64, vmx> {
+class XForm_10<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
+               dag OL, string asmstr> 
+  : XForm_base_r3xo<opcode, xo, rc, ppc64, vmx, OL, asmstr> {
   let Arg2Type = Imm5.Value;
 }
 
-class XForm_11<string name, bits<6> opcode, bits<10> xo, bit rc, bit ppc64,
-               bit vmx> : XForm_base_r3xo<name, opcode, xo, rc, ppc64, vmx> {
+class XForm_11<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
+               dag OL, string asmstr> 
+  : XForm_base_r3xo<opcode, xo, rc, ppc64, vmx, OL, asmstr> {
   let ArgCount = 2;
   let Arg2Type = 0;
   let B = 0;
@@ -355,14 +360,16 @@ class XForm_17<string name, bits<6> opcode, bits<10> xo, bit ppc64, bit vmx>
   let Inst{31}    = 0;
 }
 
-class XForm_25<string name, bits<6> opcode, bits<10> xo, bit ppc64,
-               bit vmx> : XForm_base_r3xo<name, opcode, xo, 0, ppc64, vmx> {
+class XForm_25<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
+               dag OL, string asmstr> 
+  : XForm_base_r3xo<opcode, xo, 0, ppc64, vmx, OL, asmstr> {
   let Arg0Type = Fpr.Value;
   let Arg1Type = Gpr0.Value;
 }
 
-class XForm_26<string name, bits<6> opcode, bits<10> xo, bit rc, bit ppc64,
-               bit vmx> : XForm_base_r3xo<name, opcode, xo, rc, ppc64, vmx> {
+class XForm_26<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
+               dag OL, string asmstr> 
+  : XForm_base_r3xo<opcode, xo, rc, ppc64, vmx, OL, asmstr> {
   let ArgCount = 2;
   let Arg0Type = Fpr.Value;
   let Arg1Type = Fpr.Value;
@@ -370,15 +377,17 @@ class XForm_26<string name, bits<6> opcode, bits<10> xo, bit rc, bit ppc64,
   let A = 0;
 }
 
-class XForm_28<string name, bits<6> opcode, bits<10> xo, bit ppc64,
-               bit vmx> : XForm_base_r3xo<name, opcode, xo, 0, ppc64, vmx> {
+class XForm_28<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
+               dag OL, string asmstr> 
+  : XForm_base_r3xo<opcode, xo, 0, ppc64, vmx, OL, asmstr> {
   let Arg0Type = Fpr.Value;
   let Arg1Type = Gpr0.Value;
 }
 
 // 1.7.7 XL-Form
-class XLForm_1<string name, bits<6> opcode, bits<10> xo, bit ppc64, bit vmx> 
-  : XForm_base_r3xo<name, opcode, xo, 0, ppc64, vmx> {
+class XLForm_1<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
+               dag OL, string asmstr> 
+  : XForm_base_r3xo<opcode, xo, 0, ppc64, vmx, OL, asmstr> {
   let Arg0Type = Imm5.Value;
   let Arg1Type = Imm5.Value;
   let Arg2Type = Imm5.Value;
diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index 2bf6fc2..6ef0bdd 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -22,6 +22,9 @@ class II<dag OL, string asmstr> {
   string AsmString = asmstr;
 }
 
+def u5imm   : Operand<i8> {
+  let PrintMethod = "printU5ImmOperand";
+}
 def u16imm  : Operand<i16> {
   let PrintMethod = "printU16ImmOperand";
 }
@@ -51,8 +54,6 @@ def ADDZE : XOForm_3<"addze", 31, 202, 0, 0, 0, 0>;
 def ANDIo : DForm_4<28, 0, 0,
                    (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
                    "andi. $dst, $src1, $src2">;
-def AND  : XForm_6<"and",  31, 28, 0, 0, 0>;
-def ANDC  : XForm_6<"andc",  31, 60, 0, 0, 0>;
 
 let isBranch = 1, isTerminator = 1 in {
   def COND_BRANCH : Pseudo<"COND_BRANCH">;
@@ -96,16 +97,8 @@ def CMPLDI : DForm_6_ext<10, 1, 0,
 def CMPL : XForm_16<"cmpl", 31, 32, 0, 0>;
 def CMPLW : XForm_16_ext<"cmplw", 31, 32, 0, 0>;
 def CMPLD : XForm_16_ext<"cmpld", 31, 32, 1, 0>;
-def CNTLZW : XForm_11<"cntlzw", 31, 26, 0, 0, 0>;
-def CRAND : XLForm_1<"crand", 19, 257, 0, 0>;
-def CRANDC : XLForm_1<"crandc", 19, 129, 0, 0>;
-def CRNOR : XLForm_1<"crnor", 19, 33, 0, 0>;
-def CROR : XLForm_1<"cror", 19, 449, 0, 0>;
 def DIVW : XOForm_1<"divw", 31, 491, 0, 0, 0, 0>;
 def DIVWU : XOForm_1<"divwu", 31, 459, 0, 0, 0, 0>;
-def EQV  : XForm_6<"eqv",  31, 284, 0, 0, 0>;
-def EXTSB : XForm_11<"extsb", 31, 954, 0, 0, 0>;
-def EXTSH : XForm_11<"extsh", 31, 922, 0, 0, 0>;
 def FADD : AForm_2<"fadd", 63, 21, 0, 0, 0>;
 def FADDS : AForm_2<"fadds", 59, 21, 0, 0, 0>;
 def FSUB : AForm_2<"fsub", 63, 20, 0, 0, 0>;
@@ -114,32 +107,18 @@ def FMUL : AForm_3<"fmul", 63, 25, 0, 0, 0>;
 def FMULS : AForm_3<"fmuls", 59, 25, 0, 0, 0>;
 def FDIV : AForm_2<"fdiv", 63, 18, 0, 0, 0>;
 def FDIVS : AForm_2<"fdivs", 59, 18, 0, 0, 0>;
-def FMR : XForm_26<"fmr", 63, 72, 0, 0, 0>;
-def FNEG : XForm_26<"fneg", 63, 80, 0, 0, 0>;
-def FRSP : XForm_26<"frsp", 63, 12, 0, 0, 0>;
 def FSEL : AForm_1<"fsel", 63, 23, 0, 0, 0>;
-def FCTIW : XForm_26<"fctiw", 63, 14, 0, 0, 0>;
-def FCTIWZ : XForm_26<"fctiwz", 63, 15, 0, 0, 0>;
 def FCMPU : XForm_17<"fcmpu", 63, 0, 0, 0>;
 def LBZ : DForm_1<"lbz", 35, 0, 0>;
-def LBZX : XForm_1<"lbzx", 31, 87, 0, 0>;
-def LHZ : DForm_1<"lhz", 40, 0, 0>;
-def LHZX : XForm_1<"lhzx", 31, 279, 0, 0>;
 def LHA : DForm_1<"lha", 42, 0, 0>;
-def LHAX : XForm_1<"lhax", 31, 343, 0, 0>;
+def LHZ : DForm_1<"lhz", 40, 0, 0>;
 def LWZ : DForm_1<"lwz", 32, 0, 0>;
-def LWZX : XForm_1<"lwzx", 31, 23, 0, 0>;
 def LWA : DSForm_1<"lwa", 58, 2, 1, 0>;
-def LWAX : XForm_1<"lwax", 31, 341, 1, 0>;
 def LD : DSForm_2<"ld", 58, 0, 1, 0>;
-def LDX : XForm_1<"ldx", 31, 21, 1, 0>;
 def LMW : DForm_1<"lmw", 46, 0, 0>;
 def STMW : DForm_3<"stmw", 47, 0, 0>;
 def LFS : DForm_8<"lfs", 48, 0, 0>;
-def LFSX : XForm_25<"lfsx", 31, 535, 0, 0>;
 def LFD : DForm_8<"lfd", 50, 0, 0>;
-def LFDX : XForm_25<"lfdx", 31, 599, 0, 0>;
-def MFCR : XForm_5<"mfcr", 31, 19, 0, 0>;
 def MFLR : XFXForm_1_ext<"", 31, 399, 8, 0, 0>,
                       II<(ops GPRC:$reg), "mflr $reg">;
 def MFCTR : XFXForm_1_ext<"mfctr", 31, 399, 9, 0, 0>;
@@ -148,51 +127,31 @@ def MTCTR : XFXForm_7_ext<"mtctr", 31, 467, 9, 0, 0>;
 def MULLD : XOForm_1<"mulld", 31, 233, 0, 0, 1, 0>;
 def MULLW : XOForm_1<"mullw", 31, 235, 0, 0, 0, 0>;
 def MULHWU : XOForm_2<"mulhwu", 31, 11, 0, 0, 0>;
-def NAND  : XForm_6<"nand",  31, 476, 0, 0, 0>;
 def NEG : XOForm_3<"neg", 31, 104, 0, 0, 0, 0>;
-def NOR  : XForm_6<"nor",  31, 124, 0, 0, 0>;
 def NOP : DForm_4_zero<"nop", 24, 0, 0, (ops), "nop">;
-def ORC  : XForm_6<"orc",  31, 412, 0, 0, 0>;
 def ORI  : DForm_4<24, 0, 0,
                    (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
                    "ori $dst, $src1, $src2">;
 def ORIS : DForm_4<25, 0, 0,
                    (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
                    "oris $dst, $src1, $src2">;
-def OR  : XForm_6<"or",  31, 444, 0, 0, 0>;
-def ORo : XForm_6<"or.", 31, 444, 1, 0, 0>;
 def RLDICL : MDForm_1<"rldicl", 30, 0, 0, 1, 0>;
 def RLDICR : MDForm_1<"rldicr", 30, 1, 0, 1, 0>;
 def RLWINM : MForm_2<"rlwinm", 21, 0, 0, 0>;
 def RLWNM : MForm_1<"rlwnm", 23, 0, 0, 0>;
 def RLWIMI : MForm_2<"rlwimi", 20, 0, 0, 0>;
-def SLD  : XForm_6<"sld",  31, 27, 0, 1, 0>;
-def SLW  : XForm_6<"slw",  31, 24, 0, 0, 0>;
-def SRD  : XForm_6<"srd",  31, 539, 0, 1, 0>;
-def SRW  : XForm_6<"srw",  31, 536, 0, 0, 0>;
 def SRADI  : XSForm_1<"sradi",  31, 413, 0, 1, 0>;
-def SRAWI  : XForm_10<"srawi",  31, 824, 0, 0, 0>;
-def SRAD  : XForm_6<"srad",  31, 794, 0, 1, 0>;
-def SRAW  : XForm_6<"sraw",  31, 792, 0, 0, 0>;
 def SRWI : MForm_2<"srwi", 21, 0, 0, 0>;
 def STB : DForm_3<"stb", 38, 0, 0>;
 def STBU : DForm_3<"stbu", 39, 0, 0>;
-def STBX : XForm_8<"stbx", 31, 215, 0, 0>;
 def STH : DForm_3<"sth", 44, 0, 0>;
 def STHU : DForm_3<"sthu", 45, 0, 0>;
-def STHX : XForm_8<"sthx", 31, 407, 0, 0>;
 def STW : DForm_3<"stw", 36, 0, 0>;
 def STWU : DForm_3<"stwu", 37, 0, 0>;
-def STWX : XForm_8<"stwx", 31, 151, 0, 0>;
-def STWUX : XForm_8<"stwux", 31, 183, 0, 0>;
 def STD : DSForm_2<"std", 62, 0, 1, 0>;
 def STDU : DSForm_2<"stdu", 62, 1, 1, 0>;
-def STDX : XForm_8<"stdx", 31, 149, 1, 0>;
-def STDUX : XForm_8<"stdux", 31, 181, 1, 0>;
 def STFS : DForm_9<"stfs", 52, 0, 0>;
-def STFSX : XForm_28<"stfsx", 31, 663, 0, 0>;
 def STFD : DForm_9<"stfd", 54, 0, 0>;
-def STFDX : XForm_28<"stfdx", 31, 727, 0, 0>;
 def SUBFIC : DForm_2<"subfic", 8, 0, 0>;
 def SUB : XOForm_1_rev<"sub", 31, 40, 0, 0, 0, 0>;
 def SUBF : XOForm_1<"subf", 31, 40, 0, 0, 0, 0>;
@@ -206,5 +165,93 @@ def XORI  : DForm_4<26, 0, 0,
 def XORIS : DForm_4<27, 0, 0,
                    (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
                    "xoris $dst, $src1, $src2">;
-def XOR  : XForm_6<"xor",  31, 316, 0, 0, 0>;
 def MULLI : DForm_2<"mulli", 7, 0, 0>;
+
+
+def LBZX : XForm_1<31,  87, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
+                   "lbzx $dst, $base, $index">;
+def LHAX : XForm_1<31, 343, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
+                   "lhax $dst, $base, $index">;
+def LHZX : XForm_1<31, 279, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
+                   "lhzx $dst, $base, $index">;
+def LWAX : XForm_1<31, 341, 1, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
+                   "lwax $dst, $base, $index">;
+def LWZX : XForm_1<31,  23, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
+                   "lwzx $dst, $base, $index">;
+def LDX  : XForm_1<31,  21, 1, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
+                   "ldx $dst, $base, $index">;
+def MFCR : XForm_5<31,  19, 0, 0, (ops GPRC:$dst), "mfcr $dst">;
+def AND  : XForm_6<31,  28, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
+                   "and $rA, $rS, $rB">;
+def ANDC : XForm_6<31,  60, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
+                   "andc $rA, $rS, $rB">;
+def EQV  : XForm_6<31, 284, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
+                   "eqv $rA, $rS, $rB">;
+def NAND : XForm_6<31, 476, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
+                   "nand $rA, $rS, $rB">;
+def NOR  : XForm_6<31, 124, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
+                   "nor $rA, $rS, $rB">;
+def OR   : XForm_6<31, 444, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
+                   "or $rA, $rS, $rB">;
+def ORo  : XForm_6<31, 444, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
+                   "or. $rA, $rS, $rB">;
+def ORC  : XForm_6<31, 412, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
+                   "orc $rA, $rS, $rB">;
+def SLD  : XForm_6<31,  27, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
+                   "sld $rA, $rS, $rB">;
+def SLW  : XForm_6<31,  24, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
+                   "slw $rA, $rS, $rB">;
+def SRD  : XForm_6<31, 539, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
+                   "srd $rA, $rS, $rB">;
+def SRW  : XForm_6<31, 536, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
+                   "srw $rA, $rS, $rB">;
+def SRAD : XForm_6<31, 794, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
+                   "srad $rA, $rS, $rB">;
+def SRAW : XForm_6<31, 792, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
+                   "sraw $rA, $rS, $rB">;
+def XOR  : XForm_6<31, 316, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
+                   "xor $rA, $rS, $rB">;
+def STBX  : XForm_8<31, 215, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
+                   "stbx $rS, $rA, $rB">;
+def STHX  : XForm_8<31, 407, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
+                   "sthx $rS, $rA, $rB">;
+def STWX  : XForm_8<31, 151, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
+                   "stwx $rS, $rA, $rB">;
+def STWUX : XForm_8<31, 183, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
+                   "stwux $rS, $rA, $rB">;
+def STDX  : XForm_8<31, 149, 1, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
+                   "stdx $rS, $rA, $rB">;
+def STDUX : XForm_8<31, 181, 1, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
+                   "stdux $rS, $rA, $rB">;
+def SRAWI : XForm_10<31, 824, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH), 
+                     "srawi $rA, $rS, $SH">;
+def CNTLZW : XForm_11<31,  26, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
+                      "cntlzw $rA, $rS">;
+def EXTSB  : XForm_11<31, 954, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
+                      "extsb $rA, $rS">;
+def EXTSH  : XForm_11<31, 922, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
+                      "extsh $rA, $rS">;
+def LFSX : XForm_25<31, 535, 0, 0, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
+                   "lfsx $dst, $base, $index">;
+def LFDX : XForm_25<31, 599, 0, 0, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
+                   "lfdx $dst, $base, $index">;
+def FMR    : XForm_26<63, 72, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
+                      "fmr $frD, $frB">;
+def FNEG   : XForm_26<63, 80, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
+                      "fneg $frD, $frB">;
+def FRSP   : XForm_26<63, 12, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
+                      "frsp $frD, $frB">;
+def FCTIWZ : XForm_26<63, 15, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
+                      "fctiwz $frD, $frB">;
+def STFSX : XForm_28<31, 663, 0, 0, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
+                     "stfsx $frS, $rA, $rB">;
+def STFDX : XForm_28<31, 727, 0, 0, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
+                     "stfdx $frS, $rA, $rB">;
+def CRAND  : XLForm_1<19, 257, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
+                      "crand $D, $A, $B">;
+def CRANDC : XLForm_1<19, 129, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
+                      "crandc $D, $A, $B">;
+def CRNOR  : XLForm_1<19,  33, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
+                      "crnor $D, $A, $B">;
+def CROR   : XLForm_1<19, 449, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
+                      "cror $D, $A, $B">;