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author | Chris Lattner <sabre@nondot.org> | 2010-02-12 01:55:31 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2010-02-12 01:55:31 +0000 |
commit | c96f6d606fb243f36046767b7a2c6a0dedffb139 (patch) | |
tree | 934b6c829797af0a178044bdaaac4cece31b66d6 /lib | |
parent | 3b6910dcd466bf091b386bb136f42522c89473f7 (diff) | |
download | external_llvm-c96f6d606fb243f36046767b7a2c6a0dedffb139.zip external_llvm-c96f6d606fb243f36046767b7a2c6a0dedffb139.tar.gz external_llvm-c96f6d606fb243f36046767b7a2c6a0dedffb139.tar.bz2 |
revert r95949, it turns out that adding new prefixes is not a
great solution for the disassembler, we'll go with "plan b".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95957 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/Target/X86/X86.td | 6 | ||||
-rw-r--r-- | lib/Target/X86/X86InstrInfo.h | 14 |
2 files changed, 10 insertions, 10 deletions
diff --git a/lib/Target/X86/X86.td b/lib/Target/X86/X86.td index a8f735b..7919559 100644 --- a/lib/Target/X86/X86.td +++ b/lib/Target/X86/X86.td @@ -168,11 +168,11 @@ def X86InstrInfo : InstrInfo { 6, 7, 8, + 12, 13, - 14, - 17, + 16, + 19, 20, - 21, 24]; } diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h index 7bd3e4f..a6b3863 100644 --- a/lib/Target/X86/X86InstrInfo.h +++ b/lib/Target/X86/X86InstrInfo.h @@ -291,7 +291,7 @@ namespace X86II { // set, there is no prefix byte for obtaining a multibyte opcode. // Op0Shift = 8, - Op0Mask = 0x1F << Op0Shift, + Op0Mask = 0xF << Op0Shift, // TB - TwoByte - Set if this instruction has a two byte opcode, which // starts with a 0x0F byte before the real opcode. @@ -324,13 +324,13 @@ namespace X86II { // etc. We only cares about REX.W and REX.R bits and only the former is // statically determined. // - REXShift = 13, + REXShift = 12, REX_W = 1 << REXShift, //===------------------------------------------------------------------===// // This three-bit field describes the size of an immediate operand. Zero is // unused so that we can tell if we forgot to set a value. - ImmShift = 14, + ImmShift = 13, ImmMask = 7 << ImmShift, Imm8 = 1 << ImmShift, Imm16 = 2 << ImmShift, @@ -341,7 +341,7 @@ namespace X86II { // FP Instruction Classification... Zero is non-fp instruction. // FPTypeMask - Mask for all of the FP types... - FPTypeShift = 17, + FPTypeShift = 16, FPTypeMask = 7 << FPTypeShift, // NotFP - The default, set for instructions that do not use FP registers. @@ -374,17 +374,17 @@ namespace X86II { SpecialFP = 7 << FPTypeShift, // Lock prefix - LOCKShift = 20, + LOCKShift = 19, LOCK = 1 << LOCKShift, // Segment override prefixes. Currently we just need ability to address // stuff in gs and fs segments. - SegOvrShift = 21, + SegOvrShift = 20, SegOvrMask = 3 << SegOvrShift, FS = 1 << SegOvrShift, GS = 2 << SegOvrShift, - // Bit 23 is unused. + // Bits 22 -> 23 are unused OpcodeShift = 24, OpcodeMask = 0xFF << OpcodeShift }; |