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| author | Andrew Trick <atrick@apple.com> | 2012-02-22 06:08:13 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2012-02-22 06:08:13 +0000 |
| commit | cc77b54036cfaaab9e0d9f2c731efbd2b7753cc9 (patch) | |
| tree | 2d4c9742fc34fe84337ad46426260788f8bcc67f /lib | |
| parent | b4566a999970b514d7c6973d99e293a6625d3f70 (diff) | |
| download | external_llvm-cc77b54036cfaaab9e0d9f2c731efbd2b7753cc9.zip external_llvm-cc77b54036cfaaab9e0d9f2c731efbd2b7753cc9.tar.gz external_llvm-cc77b54036cfaaab9e0d9f2c731efbd2b7753cc9.tar.bz2 | |
misched: DAG builder should not track dependencies for SSA defs.
The vast majority of virtual register definitions don't need an entry
in the DAG builder's VRegDefs set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151136 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/CodeGen/ScheduleDAGInstrs.cpp | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp index a0992c1..ddf445d 100644 --- a/lib/CodeGen/ScheduleDAGInstrs.cpp +++ b/lib/CodeGen/ScheduleDAGInstrs.cpp @@ -44,7 +44,7 @@ ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf, LoopRegs(MLI, MDT), FirstDbgValue(0) { assert((IsPostRA || LIS) && "PreRA scheduling requires LiveIntervals"); DbgValues.clear(); - assert(!(IsPostRA && MF.getRegInfo().getNumVirtRegs()) && + assert(!(IsPostRA && MRI.getNumVirtRegs()) && "Virtual registers must be removed prior to PostRA scheduling"); } @@ -361,6 +361,10 @@ void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) { const MachineInstr *MI = SU->getInstr(); unsigned Reg = MI->getOperand(OperIdx).getReg(); + // SSA defs do not have output/anti dependencies. + if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end()) + return; + // Add output dependence to the next nearest def of this vreg. // // Unless this definition is dead, the output dependence should be |