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| author | Akira Hatanaka <ahatanak@gmail.com> | 2011-07-19 20:34:00 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanak@gmail.com> | 2011-07-19 20:34:00 +0000 |
| commit | cc7ecc72909fe3f2a3eba9e7ac79cd1a13b3e8f2 (patch) | |
| tree | 3cd4b9a8a1578a4310cc25f7e17f7d56885b77c7 /lib | |
| parent | 2317fe1584e02582c616c1c4d15954999ff5525a (diff) | |
| download | external_llvm-cc7ecc72909fe3f2a3eba9e7ac79cd1a13b3e8f2.zip external_llvm-cc7ecc72909fe3f2a3eba9e7ac79cd1a13b3e8f2.tar.gz external_llvm-cc7ecc72909fe3f2a3eba9e7ac79cd1a13b3e8f2.tar.bz2 | |
Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL or
ANDi, when the instruction does not have any immediate operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135520 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/Mips/MipsISelLowering.cpp | 27 |
1 files changed, 14 insertions, 13 deletions
diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index a6579c6..b9977de 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -870,9 +870,10 @@ MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI, BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper) .addReg(Mips::ZERO).addImm(MaskImm); - BuildMI(BB, dl, TII->get(Mips::SLL), Mask).addReg(MaskUpper).addReg(ShiftAmt); + BuildMI(BB, dl, TII->get(Mips::SLLV), Mask) + .addReg(ShiftAmt).addReg(MaskUpper); BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); - BuildMI(BB, dl, TII->get(Mips::SLL), Incr2).addReg(Incr).addReg(ShiftAmt); + BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr); // atomic.load.binop @@ -911,7 +912,7 @@ MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI, BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); } else {// atomic.swap // and newval, incr2, mask - BuildMI(BB, dl, TII->get(Mips::ANDi), NewVal).addReg(Incr2).addReg(Mask); + BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask); } BuildMI(BB, dl, TII->get(Mips::AND), MaskOldVal0) @@ -933,8 +934,8 @@ MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI, BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1) .addReg(OldVal).addReg(Mask); - BuildMI(BB, dl, TII->get(Mips::SRL), SrlRes) - .addReg(MaskedOldVal1).addReg(ShiftAmt); + BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes) + .addReg(ShiftAmt).addReg(MaskedOldVal1); BuildMI(BB, dl, TII->get(Mips::SLL), SllRes) .addReg(SrlRes).addImm(ShiftImm); BuildMI(BB, dl, TII->get(Mips::SRA), Dest) @@ -1097,17 +1098,17 @@ MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI, BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper) .addReg(Mips::ZERO).addImm(MaskImm); - BuildMI(BB, dl, TII->get(Mips::SLL), Mask) - .addReg(MaskUpper).addReg(ShiftAmt); + BuildMI(BB, dl, TII->get(Mips::SLLV), Mask) + .addReg(ShiftAmt).addReg(MaskUpper); BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedCmpVal) .addReg(CmpVal).addImm(MaskImm); - BuildMI(BB, dl, TII->get(Mips::SLL), ShiftedCmpVal) - .addReg(MaskedCmpVal).addReg(ShiftAmt); + BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedCmpVal) + .addReg(ShiftAmt).addReg(MaskedCmpVal); BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedNewVal) .addReg(NewVal).addImm(MaskImm); - BuildMI(BB, dl, TII->get(Mips::SLL), ShiftedNewVal) - .addReg(MaskedNewVal).addReg(ShiftAmt); + BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedNewVal) + .addReg(ShiftAmt).addReg(MaskedNewVal); // loop1MBB: // ll oldval,0(alginedaddr) @@ -1142,8 +1143,8 @@ MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI, BB = sinkMBB; int64_t ShiftImm = (Size == 1) ? 24 : 16; - BuildMI(BB, dl, TII->get(Mips::SRL), SrlRes) - .addReg(MaskedOldVal0).addReg(ShiftAmt); + BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes) + .addReg(ShiftAmt).addReg(MaskedOldVal0); BuildMI(BB, dl, TII->get(Mips::SLL), SllRes) .addReg(SrlRes).addImm(ShiftImm); BuildMI(BB, dl, TII->get(Mips::SRA), Dest) |