FPSelect and more custom lowering

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24535 91177308-0d34-0410-b5e6-96231b3b80d8

5 files changed, 69 insertions, 25 deletions

diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
index 50ff1b0..debc41d 100644
--- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
+++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
@@ -368,8 +368,35 @@ SDOperand AlphaDAGToDAGISel::Select(SDOperand Op) {
       return FP;
     }
     break;
+
+  case ISD::SELECT:
+    if (MVT::isFloatingPoint(N->getValueType(0))) {
+      //move int to fp
+      SDOperand LD,
+        cond = Select(N->getOperand(0)),
+        TV = Select(N->getOperand(1)),
+        FV = Select(N->getOperand(2));
+      
+      if (AlphaLowering.hasITOF()) {
+        LD = CurDAG->getNode(AlphaISD::ITOFT_, MVT::f64, cond);
+      } else {
+        int FrameIdx =
+          CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
+        SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64);
+        SDOperand ST = CurDAG->getTargetNode(Alpha::STQ, MVT::Other, 
+                                             cond, FI, CurDAG->getRegister(Alpha::R31, MVT::i64));
+        LD = CurDAG->getTargetNode(Alpha::LDT, MVT::f64, FI, 
+                                   CurDAG->getRegister(Alpha::R31, MVT::i64),
+                                   ST);
+      }
+      SDOperand FP = CurDAG->getTargetNode(Alpha::FCMOVEQ, MVT::f64, TV, FV, LD);
+      return FP;
+    }
+    break;
+
+
   }
-  
+
   return SelectCode(Op);
 }
 
diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp
index 92ba16e..3ebb046 100644
--- a/lib/Target/Alpha/AlphaISelLowering.cpp
+++ b/lib/Target/Alpha/AlphaISelLowering.cpp
@@ -73,7 +73,9 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
   
   setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
   setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
-  
+  setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
+  setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
+
   if (!TM.getSubtarget<AlphaSubtarget>().hasCT()) {
     setOperationAction(ISD::CTPOP    , MVT::i64  , Expand);
     setOperationAction(ISD::CTTZ     , MVT::i64  , Expand);
@@ -412,7 +414,28 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
                                isDouble?MVT::f64:MVT::f32, LD);
     return FP;
   }
+  case ISD::FP_TO_SINT: {
+    bool isDouble = MVT::f64 == Op.getOperand(0).getValueType();
+    SDOperand src = Op.getOperand(0);
+
+    if (!isDouble) //Promote
+      src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, src);
+    
+    src = DAG.getNode(AlphaISD::CVTTQ_, MVT::f64, src);
+
+    if (useITOF) {
+      return DAG.getNode(AlphaISD::FTOIT_, MVT::i64, src);
+    } else {
+      int FrameIdx =
+        DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
+      SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
+      SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
+                                 src, FI, DAG.getSrcValue(0));
+      return DAG.getLoad(MVT::i64, ST, FI, DAG.getSrcValue(0));
+      }
   }
+
+  }
+
   return SDOperand();
 }
-
diff --git a/lib/Target/Alpha/AlphaISelLowering.h b/lib/Target/Alpha/AlphaISelLowering.h
index 378ec0f..c42dbce 100644
--- a/lib/Target/Alpha/AlphaISelLowering.h
+++ b/lib/Target/Alpha/AlphaISelLowering.h
@@ -26,7 +26,7 @@ namespace llvm {
       // Start the numbering where the builting ops and target ops leave off.
       FIRST_NUMBER = ISD::BUILTIN_OP_END+Alpha::INSTRUCTION_LIST_END,
       //These corrospond to the identical Instruction
-      ITOFT_, FTOIT_, CVTQT_, CVTQS_,
+      ITOFT_, FTOIT_, CVTQT_, CVTQS_, CVTTQ_,
     };
   }
 
diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index 05ed61f..415cd2e 100644
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -1297,26 +1297,6 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
     return Result;
   }
 
-  case ISD::FP_TO_UINT:
-  case ISD::FP_TO_SINT:
-    {
-      assert (DestType == MVT::i64 && "only quads can be loaded to");
-      MVT::ValueType SrcType = N.getOperand(0).getValueType();
-      assert (SrcType == MVT::f32 || SrcType == MVT::f64);
-      Tmp1 = SelectExpr(N.getOperand(0));  // Get the operand register
-      if (SrcType == MVT::f32)
-        {
-          Tmp2 = MakeReg(MVT::f64);
-          BuildMI(BB, Alpha::CVTST, 1, Tmp2).addReg(Tmp1);
-          Tmp1 = Tmp2;
-        }
-      Tmp2 = MakeReg(MVT::f64);
-      BuildMI(BB, Alpha::CVTTQ, 1, Tmp2).addReg(Tmp1);
-      MoveFP2Int(Tmp2, Result, true);
-
-      return Result;
-    }
-
   case ISD::SELECT:
     if (isFP) {
       //Tmp1 = SelectExpr(N.getOperand(0)); //Cond
@@ -1567,10 +1547,18 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
     BuildMI(BB, Alpha::CVTQS, 1, Result).addReg(SelectExpr(N.getOperand(0)));
     return Result;
 
+  case AlphaISD::CVTTQ_:
+    BuildMI(BB, Alpha::CVTTQ, 1, Result).addReg(SelectExpr(N.getOperand(0)));
+    return Result;
+
   case AlphaISD::ITOFT_:
     BuildMI(BB, Alpha::ITOFT, 1, Result).addReg(SelectExpr(N.getOperand(0)));
     return Result;
 
+  case AlphaISD::FTOIT_:
+    BuildMI(BB, Alpha::FTOIT, 1, Result).addReg(SelectExpr(N.getOperand(0)));
+    return Result;
+
   case ISD::AssertSext:
   case ISD::AssertZext:
     return SelectExpr(N.getOperand(0));
diff --git a/lib/Target/Alpha/AlphaInstrInfo.td b/lib/Target/Alpha/AlphaInstrInfo.td
index 6bd9d78..8cbb113 100644
--- a/lib/Target/Alpha/AlphaInstrInfo.td
+++ b/lib/Target/Alpha/AlphaInstrInfo.td
@@ -24,6 +24,7 @@ def Alpha_itoft : SDNode<"AlphaISD::ITOFT_", SDTIntToFPOp, []>;
 def Alpha_ftoit : SDNode<"AlphaISD::FTOIT_", SDTFPToIntOp, []>;
 def Alpha_cvtqt : SDNode<"AlphaISD::CVTQT_", SDTFPUnaryOpUnC, []>;
 def Alpha_cvtqs : SDNode<"AlphaISD::CVTQS_", SDTFPUnaryOpUnC, []>;
+def Alpha_cvttq : SDNode<"AlphaISD::CVTTQ_", SDTFPUnaryOp, []>;
 
 
 //********************
@@ -575,7 +576,8 @@ let OperandList = (ops F8RC:$RC, F8RC:$RB), Fa = 31 in
 def CVTQT : FPForm<0x16, 0x7BE, "cvtqt/sui $RB,$RC",
         [(set F8RC:$RC, (Alpha_cvtqt F8RC:$RB))]>;
 let OperandList = (ops F8RC:$RC, F8RC:$RB), Fa = 31 in 
-def CVTTQ : FPForm<0x16, 0x52F, "cvttq/svc $RB,$RC",[]>; //Convert T_floating to quadword
+def CVTTQ : FPForm<0x16, 0x52F, "cvttq/svc $RB,$RC",
+        [(set F8RC:$RC, (Alpha_cvttq F8RC:$RB))]>;
 let OperandList = (ops F8RC:$RC, F4RC:$RB), Fa = 31 in 
 def CVTST : FPForm<0x16, 0x6AC, "cvtst/s $RB,$RC",
                    [(set F8RC:$RC, (fextend F4RC:$RB))]>;
@@ -686,3 +688,7 @@ def : Pat<(fneg F8RC:$RB),
           (CPYSNT F8RC:$RB, F8RC:$RB)>;
 def : Pat<(fneg F4RC:$RB),
           (CPYSNS F4RC:$RB, F4RC:$RB)>;
+//Yes, signed multiply high is ugly
+def : Pat<(mulhs GPRC:$RA, GPRC:$RB),
+          (SUBQ (UMULH GPRC:$RA, GPRC:$RB), (ADDQ (CMOVGE GPRC:$RB, R31, GPRC:$RA), 
+                                                 (CMOVGE GPRC:$RA, R31, GPRC:$RB)))>;