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author | Rafael Espindola <rafael.espindola@gmail.com> | 2010-06-02 12:39:06 +0000 |
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committer | Rafael Espindola <rafael.espindola@gmail.com> | 2010-06-02 12:39:06 +0000 |
commit | ce48c1de828688b34cf5c2038fde23368a0a45f4 (patch) | |
tree | c5559e2f086c130dbe2570cbe69dd8936907a91f /lib | |
parent | 8dbbacedcd846723ac55e04c1c07882c09818b55 (diff) | |
download | external_llvm-ce48c1de828688b34cf5c2038fde23368a0a45f4.zip external_llvm-ce48c1de828688b34cf5c2038fde23368a0a45f4.tar.gz external_llvm-ce48c1de828688b34cf5c2038fde23368a0a45f4.tar.bz2 |
Remove uses of getCalleeSavedRegClasses from outside the
backends and removes the virtual declaration. With that out of the way
I should be able to cleanup one backend at a time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105321 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/CodeGen/PrologEpilogInserter.cpp | 10 | ||||
-rw-r--r-- | lib/Target/TargetRegisterInfo.cpp | 19 |
2 files changed, 22 insertions, 7 deletions
diff --git a/lib/CodeGen/PrologEpilogInserter.cpp b/lib/CodeGen/PrologEpilogInserter.cpp index e778024..d73383e 100644 --- a/lib/CodeGen/PrologEpilogInserter.cpp +++ b/lib/CodeGen/PrologEpilogInserter.cpp @@ -202,22 +202,18 @@ void PEI::calculateCalleeSavedRegisters(MachineFunction &Fn) { if (Fn.getFunction()->hasFnAttr(Attribute::Naked)) return; - // Figure out which *callee saved* registers are modified by the current - // function, thus needing to be saved and restored in the prolog/epilog. - const TargetRegisterClass * const *CSRegClasses = - RegInfo->getCalleeSavedRegClasses(&Fn); - std::vector<CalleeSavedInfo> CSI; for (unsigned i = 0; CSRegs[i]; ++i) { unsigned Reg = CSRegs[i]; + const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg); if (Fn.getRegInfo().isPhysRegUsed(Reg)) { // If the reg is modified, save it! - CSI.push_back(CalleeSavedInfo(Reg, CSRegClasses[i])); + CSI.push_back(CalleeSavedInfo(Reg, RC)); } else { for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg); *AliasSet; ++AliasSet) { // Check alias registers too. if (Fn.getRegInfo().isPhysRegUsed(*AliasSet)) { - CSI.push_back(CalleeSavedInfo(Reg, CSRegClasses[i])); + CSI.push_back(CalleeSavedInfo(Reg, RC)); break; } } diff --git a/lib/Target/TargetRegisterInfo.cpp b/lib/Target/TargetRegisterInfo.cpp index dcc5f61..32299f6 100644 --- a/lib/Target/TargetRegisterInfo.cpp +++ b/lib/Target/TargetRegisterInfo.cpp @@ -60,6 +60,25 @@ TargetRegisterInfo::getPhysicalRegisterRegClass(unsigned reg, EVT VT) const { return BestRC; } +/// getMinimalPhysRegClass - Returns the Register Class of a physical +/// register of the given type. +const TargetRegisterClass * +TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg) const { + assert(isPhysicalRegister(reg) && "reg must be a physical register"); + + // Pick the most sub register class of the right type that contains + // this physreg. + const TargetRegisterClass* BestRC = 0; + for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){ + const TargetRegisterClass* RC = *I; + if (RC->contains(reg) && (!BestRC || BestRC->hasSubClass(RC))) + BestRC = RC; + } + + assert(BestRC && "Couldn't find the register class"); + return BestRC; +} + /// getAllocatableSetForRC - Toggle the bits that represent allocatable /// registers for the specific register class. static void getAllocatableSetForRC(const MachineFunction &MF, |