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| author | Chris Lattner <sabre@nondot.org> | 2008-01-27 23:21:58 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2008-01-27 23:21:58 +0000 |
| commit | ce602f570656732a08598f43d6e7e41c01c56823 (patch) | |
| tree | f67a2a799428ff52788a181bc6acf7ff751ff38d /lib | |
| parent | 5247f17e23ea41814f194d29d0e896842277472e (diff) | |
| download | external_llvm-ce602f570656732a08598f43d6e7e41c01c56823.zip external_llvm-ce602f570656732a08598f43d6e7e41c01c56823.tar.gz external_llvm-ce602f570656732a08598f43d6e7e41c01c56823.tar.bz2 | |
fix a crash on CodeGen/X86/vector-rem.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46422 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 2c2f5e9..5d1f70f 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -1306,10 +1306,12 @@ SDOperand DAGCombiner::visitSREM(SDNode *N) { return DAG.getNode(ISD::SREM, VT, N0, N1); // If we know the sign bits of both operands are zero, strength reduce to a // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 - uint64_t SignBit = MVT::getIntVTSignBit(VT); - if (DAG.MaskedValueIsZero(N1, SignBit) && - DAG.MaskedValueIsZero(N0, SignBit)) - return DAG.getNode(ISD::UREM, VT, N0, N1); + if (!MVT::isVector(VT)) { + uint64_t SignBit = MVT::getIntVTSignBit(VT); + if (DAG.MaskedValueIsZero(N1, SignBit) && + DAG.MaskedValueIsZero(N0, SignBit)) + return DAG.getNode(ISD::UREM, VT, N0, N1); + } // If X/C can be simplified by the division-by-constant logic, lower // X%C to the equivalent of X-X/C*C. |