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author | Dale Johannesen <dalej@apple.com> | 2010-06-05 00:51:39 +0000 |
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committer | Dale Johannesen <dalej@apple.com> | 2010-06-05 00:51:39 +0000 |
commit | cf296fa1629f02e63aa1264a619a65cfc66ef173 (patch) | |
tree | ad55efcf415dbfda42c4129102478f0576b362b2 /lib | |
parent | fdbef823ad58f4ddb96da61e59ca48d8390c928f (diff) | |
download | external_llvm-cf296fa1629f02e63aa1264a619a65cfc66ef173.zip external_llvm-cf296fa1629f02e63aa1264a619a65cfc66ef173.tar.gz external_llvm-cf296fa1629f02e63aa1264a619a65cfc66ef173.tar.bz2 |
Improvements to tail call code. No functional effect
unless using -arm-tail-calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105515 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 42 |
1 files changed, 22 insertions, 20 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 5979091..6f39009 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -1259,22 +1259,8 @@ ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee, Ops.push_back(InFlag); SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); - if (isTailCall) { - // If this is the first return lowered for this function, add the regs - // to the liveout set for the function. - if (MF.getRegInfo().liveout_empty()) { - SmallVector<CCValAssign, 16> RVLocs; - CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs, - *DAG.getContext()); - CCInfo.AnalyzeCallResult(Ins, - CCAssignFnForNode(CallConv, /* Return*/ true, - isVarArg)); - for (unsigned i = 0; i != RVLocs.size(); ++i) - if (RVLocs[i].isRegLoc()) - MF.getRegInfo().addLiveOut(RVLocs[i].getLocReg()); - } + if (isTailCall) return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size()); - } // Returns a chain and a flag for retval copy to use. Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size()); @@ -1354,7 +1340,6 @@ ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const { -// const MachineFunction &MF = DAG.getMachineFunction(); const Function *CallerF = DAG.getMachineFunction().getFunction(); CallingConv::ID CallerCC = CallerF->getCallingConv(); bool CCMatch = CallerCC == CalleeCC; @@ -1427,14 +1412,31 @@ ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, const MachineRegisterInfo *MRI = &MF.getRegInfo(); const ARMInstrInfo *TII = ((ARMTargetMachine&)getTargetMachine()).getInstrInfo(); - for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { + for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); + i != e; + ++i, ++realArgIdx) { CCValAssign &VA = ArgLocs[i]; EVT RegVT = VA.getLocVT(); - SDValue Arg = Outs[i].Val; - ISD::ArgFlagsTy Flags = Outs[i].Flags; + SDValue Arg = Outs[realArgIdx].Val; + ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; if (VA.getLocInfo() == CCValAssign::Indirect) return false; - if (!VA.isRegLoc()) { + if (VA.needsCustom()) { + // f64 and vector types are split into multiple registers or + // register/stack-slot combinations. The types will not match + // the registers; give up on memory f64 refs until we figure + // out what to do about this. + if (!VA.isRegLoc()) + return false; + if (!ArgLocs[++i].isRegLoc()) + return false; + if (RegVT == MVT::v2f64) { + if (!ArgLocs[++i].isRegLoc()) + return false; + if (!ArgLocs[++i].isRegLoc()) + return false; + } + } else if (!VA.isRegLoc()) { if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, MFI, MRI, TII)) return false; |