diff options
author | Owen Anderson <resistor@mac.com> | 2007-12-31 06:32:00 +0000 |
---|---|---|
committer | Owen Anderson <resistor@mac.com> | 2007-12-31 06:32:00 +0000 |
commit | d10fd9791c20fd8368fa0ce94b626b769c6c8ba0 (patch) | |
tree | 15d4f8237ffa7600737fab617923b5bef3267b16 /lib | |
parent | f20c1a497fe3922ac718429d65a5fe396890575e (diff) | |
download | external_llvm-d10fd9791c20fd8368fa0ce94b626b769c6c8ba0.zip external_llvm-d10fd9791c20fd8368fa0ce94b626b769c6c8ba0.tar.gz external_llvm-d10fd9791c20fd8368fa0ce94b626b769c6c8ba0.tar.bz2 |
Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the
Machine-level API cleanup instigated by Chris.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45470 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
29 files changed, 312 insertions, 261 deletions
diff --git a/lib/CodeGen/LowerSubregs.cpp b/lib/CodeGen/LowerSubregs.cpp index 668a9e5..4172b12 100644 --- a/lib/CodeGen/LowerSubregs.cpp +++ b/lib/CodeGen/LowerSubregs.cpp @@ -63,6 +63,7 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) { MachineBasicBlock *MBB = MI->getParent(); MachineFunction &MF = *MBB->getParent(); const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo(); + const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); assert(MI->getOperand(0).isRegister() && MI->getOperand(0).isDef() && MI->getOperand(1).isRegister() && MI->getOperand(1).isUse() && @@ -88,7 +89,7 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) { assert(TRC == getPhysicalRegisterRegClass(MRI, SrcReg) && "Extract subreg and Dst must be of same register class"); - MRI.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC, TRC); + TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC, TRC); MachineBasicBlock::iterator dMI = MI; DOUT << "subreg: " << *(--dMI); } @@ -103,6 +104,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) { MachineBasicBlock *MBB = MI->getParent(); MachineFunction &MF = *MBB->getParent(); const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo(); + const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); unsigned DstReg = 0; unsigned SrcReg = 0; unsigned InsReg = 0; @@ -157,7 +159,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) { } else { TRC1 = MF.getRegInfo().getRegClass(InsReg); } - MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1); + TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1); #ifndef NDEBUG MachineBasicBlock::iterator dMI = MI; @@ -184,7 +186,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) { assert(TRC0 == getPhysicalRegisterRegClass(MRI, SrcReg) && "Insert superreg and Dst must be of same register class"); - MRI.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC0, TRC0); + TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC0, TRC0); #ifndef NDEBUG MachineBasicBlock::iterator dMI = MI; @@ -206,7 +208,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) { } else { TRC1 = MF.getRegInfo().getRegClass(InsReg); } - MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1); + TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1); #ifndef NDEBUG MachineBasicBlock::iterator dMI = MI; diff --git a/lib/CodeGen/PHIElimination.cpp b/lib/CodeGen/PHIElimination.cpp index 764e89b..07c4ef3 100644 --- a/lib/CodeGen/PHIElimination.cpp +++ b/lib/CodeGen/PHIElimination.cpp @@ -134,8 +134,8 @@ void PNE::LowerAtomicPHINode(MachineBasicBlock &MBB, // after any remaining phi nodes) which copies the new incoming register // into the phi node destination. // - const MRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); - RegInfo->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC, RC); + const TargetInstrInfo *TII = MF.getTarget().getInstrInfo(); + TII->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC, RC); // Update live variable information if there is any... LiveVariables *LV = getAnalysisToUpdate<LiveVariables>(); @@ -201,7 +201,7 @@ void PNE::LowerAtomicPHINode(MachineBasicBlock &MBB, MachineBasicBlock::iterator I = opBlock.getFirstTerminator(); // Insert the copy. - RegInfo->copyRegToReg(opBlock, I, IncomingReg, SrcReg, RC, RC); + TII->copyRegToReg(opBlock, I, IncomingReg, SrcReg, RC, RC); // Now update live variable information if we have it. Otherwise we're done if (!LV) continue; diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp index f506b3e..1a5387b 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp @@ -359,7 +359,7 @@ void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo, } else { // Create the reg, emit the copy. VRBase = RegInfo.createVirtualRegister(TRC); - MRI->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, TRC, TRC); + TII->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, TRC, TRC); } if (InstanceNo > 0) @@ -751,7 +751,7 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo, TRC = MRI->getPhysicalRegisterRegClass(Node->getOperand(2).getValueType(), InReg); - MRI->copyRegToReg(*BB, BB->end(), DestReg, InReg, TRC, TRC); + TII->copyRegToReg(*BB, BB->end(), DestReg, InReg, TRC, TRC); } break; } @@ -848,7 +848,7 @@ void ScheduleDAG::EmitCrossRCCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseM } } assert(I->Reg && "Unknown physical register!"); - MRI->copyRegToReg(*BB, BB->end(), Reg, VRI->second, + TII->copyRegToReg(*BB, BB->end(), Reg, VRI->second, SU->CopyDstRC, SU->CopySrcRC); } else { // Copy from physical register. @@ -856,7 +856,7 @@ void ScheduleDAG::EmitCrossRCCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseM unsigned VRBase = RegInfo.createVirtualRegister(SU->CopyDstRC); bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase)); assert(isNew && "Node emitted out of order - early"); - MRI->copyRegToReg(*BB, BB->end(), VRBase, I->Reg, + TII->copyRegToReg(*BB, BB->end(), VRBase, I->Reg, SU->CopyDstRC, SU->CopySrcRC); } break; @@ -874,7 +874,7 @@ void ScheduleDAG::EmitSchedule() { E = RegInfo.livein_end(); LI != E; ++LI) if (LI->second) { const TargetRegisterClass *RC = RegInfo.getRegClass(LI->second); - MRI->copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second, + TII->copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second, LI->first, RC, RC); } } diff --git a/lib/CodeGen/TwoAddressInstructionPass.cpp b/lib/CodeGen/TwoAddressInstructionPass.cpp index 4f92bdb..dd71bec 100644 --- a/lib/CodeGen/TwoAddressInstructionPass.cpp +++ b/lib/CodeGen/TwoAddressInstructionPass.cpp @@ -80,7 +80,6 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) { DOUT << "Machine Function\n"; const TargetMachine &TM = MF.getTarget(); const TargetInstrInfo &TII = *TM.getInstrInfo(); - const MRegisterInfo &MRI = *TM.getRegisterInfo(); LiveVariables &LV = getAnalysis<LiveVariables>(); bool MadeChange = false; @@ -193,7 +192,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) { InstructionRearranged: const TargetRegisterClass* rc = MF.getRegInfo().getRegClass(regA); - MRI.copyRegToReg(*mbbi, mi, regA, regB, rc, rc); + TII.copyRegToReg(*mbbi, mi, regA, regB, rc, rc); MachineBasicBlock::iterator prevMi = prior(mi); DOUT << "\t\tprepend:\t"; DEBUG(prevMi->print(*cerr.stream(), &TM)); diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp index 9100054..dc21518 100644 --- a/lib/CodeGen/VirtRegMap.cpp +++ b/lib/CodeGen/VirtRegMap.cpp @@ -928,7 +928,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { DOUT << MBB.getBasicBlock()->getName() << ":\n"; MachineFunction &MF = *MBB.getParent(); - + // Spills - Keep track of which spilled values are available in physregs so // that we can choose to reuse the physregs instead of emitting reloads. AvailableSpills Spills(MRI, TII); @@ -1182,7 +1182,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg); RegInfo->setPhysRegUsed(DesignatedReg); ReusedOperands.markClobbered(DesignatedReg); - MRI->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC, RC); + TII->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC, RC); MachineInstr *CopyMI = prior(MII); UpdateKills(*CopyMI, RegKills, KillOps); @@ -1268,7 +1268,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { DOUT << "Promoted Load To Copy: " << MI; if (DestReg != InReg) { const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg); - MRI->copyRegToReg(MBB, &MI, DestReg, InReg, RC, RC); + TII->copyRegToReg(MBB, &MI, DestReg, InReg, RC, RC); // Revisit the copy so we make sure to notice the effects of the // operation on the destreg (either needing to RA it if it's // virtual or needing to clobber any values if it's physical). diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp index da72193..b2c0649 100644 --- a/lib/Target/ARM/ARMInstrInfo.cpp +++ b/lib/Target/ARM/ARMInstrInfo.cpp @@ -27,6 +27,16 @@ using namespace llvm; static cl::opt<bool> EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden, cl::desc("Enable ARM 2-addr to 3-addr conv")); +static inline +const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) { + return MIB.addImm((int64_t)ARMCC::AL).addReg(0); +} + +static inline +const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) { + return MIB.addReg(0); +} + ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI) : TargetInstrInfo(ARMInsts, array_lengthof(ARMInsts)), RI(*this, STI) { @@ -432,6 +442,34 @@ unsigned ARMInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *T return 2; } +void ARMInstrInfo::copyRegToReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const { + if (DestRC != SrcRC) { + cerr << "Not yet supported!"; + abort(); + } + + if (DestRC == ARM::GPRRegisterClass) { + MachineFunction &MF = *MBB.getParent(); + ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); + if (AFI->isThumbFunction()) + BuildMI(MBB, I, get(ARM::tMOVr), DestReg).addReg(SrcReg); + else + AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, get(ARM::MOVr), DestReg) + .addReg(SrcReg))); + } else if (DestRC == ARM::SPRRegisterClass) + AddDefaultPred(BuildMI(MBB, I, get(ARM::FCPYS), DestReg) + .addReg(SrcReg)); + else if (DestRC == ARM::DPRRegisterClass) + AddDefaultPred(BuildMI(MBB, I, get(ARM::FCPYD), DestReg) + .addReg(SrcReg)); + else + abort(); +} + bool ARMInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const { if (MBB.empty()) return false; diff --git a/lib/Target/ARM/ARMInstrInfo.h b/lib/Target/ARM/ARMInstrInfo.h index 7afc3b2..4951ad4 100644 --- a/lib/Target/ARM/ARMInstrInfo.h +++ b/lib/Target/ARM/ARMInstrInfo.h @@ -160,6 +160,11 @@ public: virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const std::vector<MachineOperand> &Cond) const; + virtual void copyRegToReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const; virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const; virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const; diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp index 8328cef..b9c0242 100644 --- a/lib/Target/ARM/ARMRegisterInfo.cpp +++ b/lib/Target/ARM/ARMRegisterInfo.cpp @@ -270,34 +270,6 @@ void ARMRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, return; } -void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *DestRC, - const TargetRegisterClass *SrcRC) const { - if (DestRC != SrcRC) { - cerr << "Not yet supported!"; - abort(); - } - - if (DestRC == ARM::GPRRegisterClass) { - MachineFunction &MF = *MBB.getParent(); - ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); - if (AFI->isThumbFunction()) - BuildMI(MBB, I, TII.get(ARM::tMOVr), DestReg).addReg(SrcReg); - else - AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::MOVr), DestReg) - .addReg(SrcReg))); - } else if (DestRC == ARM::SPRRegisterClass) - AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::FCPYS), DestReg) - .addReg(SrcReg)); - else if (DestRC == ARM::DPRRegisterClass) - AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::FCPYD), DestReg) - .addReg(SrcReg)); - else - abort(); -} - /// emitLoadConstPool - Emits a load from constpool to materialize the /// specified immediate. static void emitLoadConstPool(MachineBasicBlock &MBB, diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp index aa7d10a..db0dc7b 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.cpp +++ b/lib/Target/Alpha/AlphaInstrInfo.cpp @@ -132,6 +132,29 @@ unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock * return 2; } +void AlphaInstrInfo::copyRegToReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const { + //cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n"; + if (DestRC != SrcRC) { + cerr << "Not yet supported!"; + abort(); + } + + if (DestRC == Alpha::GPRCRegisterClass) { + BuildMI(MBB, MI, get(Alpha::BISr), DestReg).addReg(SrcReg).addReg(SrcReg); + } else if (DestRC == Alpha::F4RCRegisterClass) { + BuildMI(MBB, MI, get(Alpha::CPYSS), DestReg).addReg(SrcReg).addReg(SrcReg); + } else if (DestRC == Alpha::F8RCRegisterClass) { + BuildMI(MBB, MI, get(Alpha::CPYST), DestReg).addReg(SrcReg).addReg(SrcReg); + } else { + cerr << "Attempt to copy register that is not GPR or FPR"; + abort(); + } +} + static unsigned AlphaRevCondCode(unsigned Opcode) { switch (Opcode) { case Alpha::BEQ: return Alpha::BNE; diff --git a/lib/Target/Alpha/AlphaInstrInfo.h b/lib/Target/Alpha/AlphaInstrInfo.h index 649d9c5..7ce377a 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.h +++ b/lib/Target/Alpha/AlphaInstrInfo.h @@ -42,6 +42,11 @@ public: virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const std::vector<MachineOperand> &Cond) const; + virtual void copyRegToReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const; bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, std::vector<MachineOperand> &Cond) const; diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp index 490d1ad..be9cbf5 100644 --- a/lib/Target/Alpha/AlphaRegisterInfo.cpp +++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp @@ -190,30 +190,6 @@ MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI, return 0; } - -void AlphaRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *DestRC, - const TargetRegisterClass *SrcRC) const { - //cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n"; - if (DestRC != SrcRC) { - cerr << "Not yet supported!"; - abort(); - } - - if (DestRC == Alpha::GPRCRegisterClass) { - BuildMI(MBB, MI, TII.get(Alpha::BISr), DestReg).addReg(SrcReg).addReg(SrcReg); - } else if (DestRC == Alpha::F4RCRegisterClass) { - BuildMI(MBB, MI, TII.get(Alpha::CPYSS), DestReg).addReg(SrcReg).addReg(SrcReg); - } else if (DestRC == Alpha::F8RCRegisterClass) { - BuildMI(MBB, MI, TII.get(Alpha::CPYST), DestReg).addReg(SrcReg).addReg(SrcReg); - } else { - cerr << "Attempt to copy register that is not GPR or FPR"; - abort(); - } -} - void AlphaRegisterInfo::reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp index 1b321b6..0e5c505 100644 --- a/lib/Target/CellSPU/SPUInstrInfo.cpp +++ b/lib/Target/CellSPU/SPUInstrInfo.cpp @@ -180,3 +180,40 @@ SPUInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const { } return 0; } + +void SPUInstrInfo::copyRegToReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const +{ + if (DestRC != SrcRC) { + cerr << "SPURegisterInfo::copyRegToReg(): DestRC != SrcRC not supported!\n"; + abort(); + } + + if (DestRC == SPU::R8CRegisterClass) { + BuildMI(MBB, MI, get(SPU::ORBIr8), DestReg).addReg(SrcReg).addImm(0); + } else if (DestRC == SPU::R16CRegisterClass) { + BuildMI(MBB, MI, get(SPU::ORHIr16), DestReg).addReg(SrcReg).addImm(0); + } else if (DestRC == SPU::R32CRegisterClass) { + BuildMI(MBB, MI, get(SPU::ORIr32), DestReg).addReg(SrcReg).addImm(0); + } else if (DestRC == SPU::R32FPRegisterClass) { + BuildMI(MBB, MI, get(SPU::ORf32), DestReg).addReg(SrcReg) + .addReg(SrcReg); + } else if (DestRC == SPU::R64CRegisterClass) { + BuildMI(MBB, MI, get(SPU::ORIr64), DestReg).addReg(SrcReg).addImm(0); + } else if (DestRC == SPU::R64FPRegisterClass) { + BuildMI(MBB, MI, get(SPU::ORf64), DestReg).addReg(SrcReg) + .addReg(SrcReg); + } else if (DestRC == SPU::GPRCRegisterClass) { + BuildMI(MBB, MI, get(SPU::ORgprc), DestReg).addReg(SrcReg) + .addReg(SrcReg); + } else if (DestRC == SPU::VECREGRegisterClass) { + BuildMI(MBB, MI, get(SPU::ORv4i32), DestReg).addReg(SrcReg) + .addReg(SrcReg); + } else { + std::cerr << "Attempt to copy unknown/unsupported register class!\n"; + abort(); + } +} diff --git a/lib/Target/CellSPU/SPUInstrInfo.h b/lib/Target/CellSPU/SPUInstrInfo.h index ffc922a..e998651 100644 --- a/lib/Target/CellSPU/SPUInstrInfo.h +++ b/lib/Target/CellSPU/SPUInstrInfo.h @@ -46,6 +46,12 @@ namespace llvm { unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const; unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const; + + virtual void copyRegToReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const; }; } diff --git a/lib/Target/CellSPU/SPURegisterInfo.cpp b/lib/Target/CellSPU/SPURegisterInfo.cpp index ec886d5..a05ab41 100644 --- a/lib/Target/CellSPU/SPURegisterInfo.cpp +++ b/lib/Target/CellSPU/SPURegisterInfo.cpp @@ -360,43 +360,6 @@ void SPURegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, } } -void SPURegisterInfo::copyRegToReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *DestRC, - const TargetRegisterClass *SrcRC) const -{ - if (DestRC != SrcRC) { - cerr << "SPURegisterInfo::copyRegToReg(): DestRC != SrcRC not supported!\n"; - abort(); - } - - if (DestRC == SPU::R8CRegisterClass) { - BuildMI(MBB, MI, TII.get(SPU::ORBIr8), DestReg).addReg(SrcReg).addImm(0); - } else if (DestRC == SPU::R16CRegisterClass) { - BuildMI(MBB, MI, TII.get(SPU::ORHIr16), DestReg).addReg(SrcReg).addImm(0); - } else if (DestRC == SPU::R32CRegisterClass) { - BuildMI(MBB, MI, TII.get(SPU::ORIr32), DestReg).addReg(SrcReg).addImm(0); - } else if (DestRC == SPU::R32FPRegisterClass) { - BuildMI(MBB, MI, TII.get(SPU::ORf32), DestReg).addReg(SrcReg) - .addReg(SrcReg); - } else if (DestRC == SPU::R64CRegisterClass) { - BuildMI(MBB, MI, TII.get(SPU::ORIr64), DestReg).addReg(SrcReg).addImm(0); - } else if (DestRC == SPU::R64FPRegisterClass) { - BuildMI(MBB, MI, TII.get(SPU::ORf64), DestReg).addReg(SrcReg) - .addReg(SrcReg); - } else if (DestRC == SPU::GPRCRegisterClass) { - BuildMI(MBB, MI, TII.get(SPU::ORgprc), DestReg).addReg(SrcReg) - .addReg(SrcReg); - } else if (DestRC == SPU::VECREGRegisterClass) { - BuildMI(MBB, MI, TII.get(SPU::ORv4i32), DestReg).addReg(SrcReg) - .addReg(SrcReg); - } else { - std::cerr << "Attempt to copy unknown/unsupported register class!\n"; - abort(); - } -} - void SPURegisterInfo::reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, diff --git a/lib/Target/IA64/IA64InstrInfo.cpp b/lib/Target/IA64/IA64InstrInfo.cpp index 7f7d895..ea3336c 100644 --- a/lib/Target/IA64/IA64InstrInfo.cpp +++ b/lib/Target/IA64/IA64InstrInfo.cpp @@ -56,3 +56,21 @@ IA64InstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, BuildMI(&MBB, get(IA64::BRL_NOTCALL)).addMBB(TBB); return 1; } + +void IA64InstrInfo::copyRegToReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const { + if (DestRC != SrcRC) { + cerr << "Not yet supported!"; + abort(); + } + + if(DestRC == IA64::PRRegisterClass ) // if a bool, we use pseudocode + // (SrcReg) DestReg = cmp.eq.unc(r0, r0) + BuildMI(MBB, MI, get(IA64::PCMPEQUNC), DestReg) + .addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg); + else // otherwise, MOV works (for both gen. regs and FP regs) + BuildMI(MBB, MI, get(IA64::MOV), DestReg).addReg(SrcReg); +} diff --git a/lib/Target/IA64/IA64InstrInfo.h b/lib/Target/IA64/IA64InstrInfo.h index 3b04dd1..07a98a5 100644 --- a/lib/Target/IA64/IA64InstrInfo.h +++ b/lib/Target/IA64/IA64InstrInfo.h @@ -40,7 +40,11 @@ public: virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const std::vector<MachineOperand> &Cond) const; - + virtual void copyRegToReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const; }; } // End llvm namespace diff --git a/lib/Target/IA64/IA64RegisterInfo.cpp b/lib/Target/IA64/IA64RegisterInfo.cpp index b570824..68f743e 100644 --- a/lib/Target/IA64/IA64RegisterInfo.cpp +++ b/lib/Target/IA64/IA64RegisterInfo.cpp @@ -144,24 +144,6 @@ void IA64RegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, return; } -void IA64RegisterInfo::copyRegToReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *DestRC, - const TargetRegisterClass *SrcRC) const { - if (DestRC != SrcRC) { - cerr << "Not yet supported!"; - abort(); - } - - if(DestRC == IA64::PRRegisterClass ) // if a bool, we use pseudocode - // (SrcReg) DestReg = cmp.eq.unc(r0, r0) - BuildMI(MBB, MI, TII.get(IA64::PCMPEQUNC), DestReg) - .addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg); - else // otherwise, MOV works (for both gen. regs and FP regs) - BuildMI(MBB, MI, TII.get(IA64::MOV), DestReg).addReg(SrcReg); -} - void IA64RegisterInfo::reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp index 1afa216..17d30b6 100644 --- a/lib/Target/Mips/MipsInstrInfo.cpp +++ b/lib/Target/Mips/MipsInstrInfo.cpp @@ -289,6 +289,23 @@ InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, return 2; } +void MipsInstrInfo:: +copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const { + if (DestRC != SrcRC) { + cerr << "Not yet supported!"; + abort(); + } + + if (DestRC == Mips::CPURegsRegisterClass) + BuildMI(MBB, I, get(Mips::ADDu), DestReg).addReg(Mips::ZERO) + .addReg(SrcReg); + else + assert (0 && "Can't copy this register"); +} + unsigned MipsInstrInfo:: RemoveBranch(MachineBasicBlock &MBB) const { diff --git a/lib/Target/Mips/MipsInstrInfo.h b/lib/Target/Mips/MipsInstrInfo.h index 2fc2afe..ee63a4a 100644 --- a/lib/Target/Mips/MipsInstrInfo.h +++ b/lib/Target/Mips/MipsInstrInfo.h @@ -83,6 +83,10 @@ public: virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const std::vector<MachineOperand> &Cond) const; + virtual void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const; virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const; virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const; diff --git a/lib/Target/Mips/MipsRegisterInfo.cpp b/lib/Target/Mips/MipsRegisterInfo.cpp index d526699..2930b59 100644 --- a/lib/Target/Mips/MipsRegisterInfo.cpp +++ b/lib/Target/Mips/MipsRegisterInfo.cpp @@ -148,24 +148,6 @@ void MipsRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, return; } -void MipsRegisterInfo:: -copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, - unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *DestRC, - const TargetRegisterClass *SrcRC) const -{ - if (DestRC != SrcRC) { - cerr << "Not yet supported!"; - abort(); - } - - if (DestRC == Mips::CPURegsRegisterClass) - BuildMI(MBB, I, TII.get(Mips::ADDu), DestReg).addReg(Mips::ZERO) - .addReg(SrcReg); - else - assert (0 && "Can't copy this register"); -} - void MipsRegisterInfo::reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp index 6652ea4..327622f 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -277,6 +277,34 @@ PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, return 2; } +void PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const { + if (DestRC != SrcRC) { + cerr << "Not yet supported!"; + abort(); + } + + if (DestRC == PPC::GPRCRegisterClass) { + BuildMI(MBB, MI, get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg); + } else if (DestRC == PPC::G8RCRegisterClass) { + BuildMI(MBB, MI, get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg); + } else if (DestRC == PPC::F4RCRegisterClass) { + BuildMI(MBB, MI, get(PPC::FMRS), DestReg).addReg(SrcReg); + } else if (DestRC == PPC::F8RCRegisterClass) { + BuildMI(MBB, MI, get(PPC::FMRD), DestReg).addReg(SrcReg); + } else if (DestRC == PPC::CRRCRegisterClass) { + BuildMI(MBB, MI, get(PPC::MCRF), DestReg).addReg(SrcReg); + } else if (DestRC == PPC::VRRCRegisterClass) { + BuildMI(MBB, MI, get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg); + } else { + cerr << "Attempt to copy register that is not GPR or FPR"; + abort(); + } +} + bool PPCInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const { if (MBB.empty()) return false; diff --git a/lib/Target/PowerPC/PPCInstrInfo.h b/lib/Target/PowerPC/PPCInstrInfo.h index 47cb42b..f511e23 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.h +++ b/lib/Target/PowerPC/PPCInstrInfo.h @@ -103,6 +103,11 @@ public: virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const std::vector<MachineOperand> &Cond) const; + void copyRegToReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const; virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const; virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const; }; diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index 3c8bc9f..173b29e 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -332,34 +332,6 @@ void PPCRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, return; } -void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *DestRC, - const TargetRegisterClass *SrcRC) const { - if (DestRC != SrcRC) { - cerr << "Not yet supported!"; - abort(); - } - - if (DestRC == PPC::GPRCRegisterClass) { - BuildMI(MBB, MI, TII.get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg); - } else if (DestRC == PPC::G8RCRegisterClass) { - BuildMI(MBB, MI, TII.get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg); - } else if (DestRC == PPC::F4RCRegisterClass) { - BuildMI(MBB, MI, TII.get(PPC::FMRS), DestReg).addReg(SrcReg); - } else if (DestRC == PPC::F8RCRegisterClass) { - BuildMI(MBB, MI, TII.get(PPC::FMRD), DestReg).addReg(SrcReg); - } else if (DestRC == PPC::CRRCRegisterClass) { - BuildMI(MBB, MI, TII.get(PPC::MCRF), DestReg).addReg(SrcReg); - } else if (DestRC == PPC::VRRCRegisterClass) { - BuildMI(MBB, MI, TII.get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg); - } else { - cerr << "Attempt to copy register that is not GPR or FPR"; - abort(); - } -} - void PPCRegisterInfo::reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, diff --git a/lib/Target/Sparc/SparcInstrInfo.cpp b/lib/Target/Sparc/SparcInstrInfo.cpp index 86af68d..5a64a44 100644 --- a/lib/Target/Sparc/SparcInstrInfo.cpp +++ b/lib/Target/Sparc/SparcInstrInfo.cpp @@ -12,6 +12,7 @@ //===----------------------------------------------------------------------===// #include "SparcInstrInfo.h" +#include "SparcSubtarget.h" #include "Sparc.h" #include "llvm/ADT/STLExtras.h" #include "llvm/CodeGen/MachineInstrBuilder.h" @@ -20,7 +21,7 @@ using namespace llvm; SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST) : TargetInstrInfo(SparcInsts, array_lengthof(SparcInsts)), - RI(ST, *this) { + RI(ST, *this), Subtarget(ST) { } static bool isZeroImm(const MachineOperand &op) { @@ -107,3 +108,24 @@ SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, BuildMI(&MBB, get(SP::BA)).addMBB(TBB); return 1; } + +void SparcInstrInfo::copyRegToReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const { + if (DestRC != SrcRC) { + cerr << "Not yet supported!"; + abort(); + } + + if (DestRC == SP::IntRegsRegisterClass) + BuildMI(MBB, I, get(SP::ORrr), DestReg).addReg(SP::G0).addReg(SrcReg); + else if (DestRC == SP::FPRegsRegisterClass) + BuildMI(MBB, I, get(SP::FMOVS), DestReg).addReg(SrcReg); + else if (DestRC == SP::DFPRegsRegisterClass) + BuildMI(MBB, I, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD),DestReg) + .addReg(SrcReg); + else + assert (0 && "Can't copy this register"); +} diff --git a/lib/Target/Sparc/SparcInstrInfo.h b/lib/Target/Sparc/SparcInstrInfo.h index 0da80a9..16540ab 100644 --- a/lib/Target/Sparc/SparcInstrInfo.h +++ b/lib/Target/Sparc/SparcInstrInfo.h @@ -33,6 +33,7 @@ namespace SPII { class SparcInstrInfo : public TargetInstrInfo { const SparcRegisterInfo RI; + const SparcSubtarget& Subtarget; public: SparcInstrInfo(SparcSubtarget &ST); @@ -66,6 +67,12 @@ public: virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const std::vector<MachineOperand> &Cond) const; + + virtual void copyRegToReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const; }; } diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp index 7416ebb..3cc234f 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.cpp +++ b/lib/Target/Sparc/SparcRegisterInfo.cpp @@ -122,27 +122,6 @@ void SparcRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, return; } -void SparcRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *DestRC, - const TargetRegisterClass *SrcRC) const { - if (DestRC != SrcRC) { - cerr << "Not yet supported!"; - abort(); - } - - if (DestRC == SP::IntRegsRegisterClass) - BuildMI(MBB, I, TII.get(SP::ORrr), DestReg).addReg(SP::G0).addReg(SrcReg); - else if (DestRC == SP::FPRegsRegisterClass) - BuildMI(MBB, I, TII.get(SP::FMOVS), DestReg).addReg(SrcReg); - else if (DestRC == SP::DFPRegsRegisterClass) - BuildMI(MBB, I, TII.get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD),DestReg) - .addReg(SrcReg); - else - assert (0 && "Can't copy this register"); -} - void SparcRegisterInfo::reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index 3470baa..76979d8 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -784,6 +784,74 @@ X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, return 2; } +void X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const { + if (DestRC != SrcRC) { + // Moving EFLAGS to / from another register requires a push and a pop. + if (SrcRC == &X86::CCRRegClass) { + assert(SrcReg == X86::EFLAGS); + if (DestRC == &X86::GR64RegClass) { + BuildMI(MBB, MI, get(X86::PUSHFQ)); + BuildMI(MBB, MI, get(X86::POP64r), DestReg); + return; + } else if (DestRC == &X86::GR32RegClass) { + BuildMI(MBB, MI, get(X86::PUSHFD)); + BuildMI(MBB, MI, get(X86::POP32r), DestReg); + return; + } + } else if (DestRC == &X86::CCRRegClass) { + assert(DestReg == X86::EFLAGS); + if (SrcRC == &X86::GR64RegClass) { + BuildMI(MBB, MI, get(X86::PUSH64r)).addReg(SrcReg); + BuildMI(MBB, MI, get(X86::POPFQ)); + return; + } else if (SrcRC == &X86::GR32RegClass) { + BuildMI(MBB, MI, get(X86::PUSH32r)).addReg(SrcReg); + BuildMI(MBB, MI, get(X86::POPFD)); + return; + } + } + cerr << "Not yet supported!"; + abort(); + } + + unsigned Opc; + if (DestRC == &X86::GR64RegClass) { + Opc = X86::MOV64rr; + } else if (DestRC == &X86::GR32RegClass) { + Opc = X86::MOV32rr; + } else if (DestRC == &X86::GR16RegClass) { + Opc = X86::MOV16rr; + } else if (DestRC == &X86::GR8RegClass) { + Opc = X86::MOV8rr; + } else if (DestRC == &X86::GR32_RegClass) { + Opc = X86::MOV32_rr; + } else if (DestRC == &X86::GR16_RegClass) { + Opc = X86::MOV16_rr; + } else if (DestRC == &X86::RFP32RegClass) { + Opc = X86::MOV_Fp3232; + } else if (DestRC == &X86::RFP64RegClass || DestRC == &X86::RSTRegClass) { + Opc = X86::MOV_Fp6464; + } else if (DestRC == &X86::RFP80RegClass) { + Opc = X86::MOV_Fp8080; + } else if (DestRC == &X86::FR32RegClass) { + Opc = X86::FsMOVAPSrr; + } else if (DestRC == &X86::FR64RegClass) { + Opc = X86::FsMOVAPDrr; + } else if (DestRC == &X86::VR128RegClass) { + Opc = X86::MOVAPSrr; + } else if (DestRC == &X86::VR64RegClass) { + Opc = X86::MMX_MOVQ64rr; + } else { + assert(0 && "Unknown regclass"); + abort(); + } + BuildMI(MBB, MI, get(Opc), DestReg).addReg(SrcReg); +} + bool X86InstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const { if (MBB.empty()) return false; diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h index 589edac..88df882 100644 --- a/lib/Target/X86/X86InstrInfo.h +++ b/lib/Target/X86/X86InstrInfo.h @@ -279,6 +279,11 @@ public: virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const std::vector<MachineOperand> &Cond) const; + virtual void copyRegToReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const; virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const; virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const; diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index 788bcc6..b320366 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -916,74 +916,6 @@ void X86RegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, NewMIs.push_back(MIB); } -void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *DestRC, - const TargetRegisterClass *SrcRC) const { - if (DestRC != SrcRC) { - // Moving EFLAGS to / from another register requires a push and a pop. - if (SrcRC == &X86::CCRRegClass) { - assert(SrcReg == X86::EFLAGS); - if (DestRC == &X86::GR64RegClass) { - BuildMI(MBB, MI, TII.get(X86::PUSHFQ)); - BuildMI(MBB, MI, TII.get(X86::POP64r), DestReg); - return; - } else if (DestRC == &X86::GR32RegClass) { - BuildMI(MBB, MI, TII.get(X86::PUSHFD)); - BuildMI(MBB, MI, TII.get(X86::POP32r), DestReg); - return; - } - } else if (DestRC == &X86::CCRRegClass) { - assert(DestReg == X86::EFLAGS); - if (SrcRC == &X86::GR64RegClass) { - BuildMI(MBB, MI, TII.get(X86::PUSH64r)).addReg(SrcReg); - BuildMI(MBB, MI, TII.get(X86::POPFQ)); - return; - } else if (SrcRC == &X86::GR32RegClass) { - BuildMI(MBB, MI, TII.get(X86::PUSH32r)).addReg(SrcReg); - BuildMI(MBB, MI, TII.get(X86::POPFD)); - return; - } - } - cerr << "Not yet supported!"; - abort(); - } - - unsigned Opc; - if (DestRC == &X86::GR64RegClass) { - Opc = X86::MOV64rr; - } else if (DestRC == &X86::GR32RegClass) { - Opc = X86::MOV32rr; - } else if (DestRC == &X86::GR16RegClass) { - Opc = X86::MOV16rr; - } else if (DestRC == &X86::GR8RegClass) { - Opc = X86::MOV8rr; - } else if (DestRC == &X86::GR32_RegClass) { - Opc = X86::MOV32_rr; - } else if (DestRC == &X86::GR16_RegClass) { - Opc = X86::MOV16_rr; - } else if (DestRC == &X86::RFP32RegClass) { - Opc = X86::MOV_Fp3232; - } else if (DestRC == &X86::RFP64RegClass || DestRC == &X86::RSTRegClass) { - Opc = X86::MOV_Fp6464; - } else if (DestRC == &X86::RFP80RegClass) { - Opc = X86::MOV_Fp8080; - } else if (DestRC == &X86::FR32RegClass) { - Opc = X86::FsMOVAPSrr; - } else if (DestRC == &X86::FR64RegClass) { - Opc = X86::FsMOVAPDrr; - } else if (DestRC == &X86::VR128RegClass) { - Opc = X86::MOVAPSrr; - } else if (DestRC == &X86::VR64RegClass) { - Opc = X86::MMX_MOVQ64rr; - } else { - assert(0 && "Unknown regclass"); - abort(); - } - BuildMI(MBB, MI, TII.get(Opc), DestReg).addReg(SrcReg); -} - const TargetRegisterClass * X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { if (RC == &X86::CCRRegClass) |