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| author | Evan Cheng <evan.cheng@apple.com> | 2009-11-02 07:58:25 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2009-11-02 07:58:25 +0000 |
| commit | d3e18fad7e7c6839a3d343f77957a488754d06b6 (patch) | |
| tree | 6e60f47cd5c0bdf51728dc21ab3c4987bec671e2 /lib | |
| parent | e3b88fc01e64200c3685c1b14eb23a3f4625edf2 (diff) | |
| download | external_llvm-d3e18fad7e7c6839a3d343f77957a488754d06b6.zip external_llvm-d3e18fad7e7c6839a3d343f77957a488754d06b6.tar.gz external_llvm-d3e18fad7e7c6839a3d343f77957a488754d06b6.tar.bz2 | |
These are done / no longer care.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85798 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/ARM/README.txt | 21 |
1 files changed, 0 insertions, 21 deletions
diff --git a/lib/Target/ARM/README.txt b/lib/Target/ARM/README.txt index 6e5a7a1..fb64d9f 100644 --- a/lib/Target/ARM/README.txt +++ b/lib/Target/ARM/README.txt @@ -8,12 +8,8 @@ Reimplement 'select' in terms of 'SEL'. add doesn't need to overflow between the two 16-bit chunks. * Implement pre/post increment support. (e.g. PR935) -* Coalesce stack slots! * Implement smarter constant generation for binops with large immediates. -* Consider materializing FP constants like 0.0f and 1.0f using integer - immediate instructions then copy to FPU. Slower than load into FPU? - //===---------------------------------------------------------------------===// Crazy idea: Consider code that uses lots of 8-bit or 16-bit values. By the @@ -422,14 +418,6 @@ are not remembered when the same two values are compared twice. //===---------------------------------------------------------------------===// -More register scavenging work: - -1. Use the register scavenger to track frame index materialized into registers - (those that do not fit in addressing modes) to allow reuse in the same BB. -2. Finish scavenging for Thumb. - -//===---------------------------------------------------------------------===// - More LSR enhancements possible: 1. Teach LSR about pre- and post- indexed ops to allow iv increment be merged @@ -540,10 +528,6 @@ while ARMConstantIslandPass only need to worry about LDR (literal). //===---------------------------------------------------------------------===// -We need to fix constant isel for ARMv6t2 to use MOVT. - -//===---------------------------------------------------------------------===// - Constant island pass should make use of full range SoImm values for LEApcrel. Be careful though as the last attempt caused infinite looping on lencod. @@ -593,11 +577,6 @@ it saves an instruction and a register. //===---------------------------------------------------------------------===// -add/sub/and/or + i32 imm can be simplified by folding part of the immediate -into the operation. - -//===---------------------------------------------------------------------===// - It might be profitable to cse MOVi16 if there are lots of 32-bit immediates with the same bottom half. |