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author | Akira Hatanaka <ahatanaka@mips.com> | 2013-07-01 20:31:44 +0000 |
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committer | Akira Hatanaka <ahatanaka@mips.com> | 2013-07-01 20:31:44 +0000 |
commit | db8e0bbedb46c9f781f8a32728b1019f34089ed8 (patch) | |
tree | 96b227e24c3487d12b99961e0a559adead2def4e /lib | |
parent | ae99e41ff45b0fdd432975f8e7763167b57bcaf5 (diff) | |
download | external_llvm-db8e0bbedb46c9f781f8a32728b1019f34089ed8.zip external_llvm-db8e0bbedb46c9f781f8a32728b1019f34089ed8.tar.gz external_llvm-db8e0bbedb46c9f781f8a32728b1019f34089ed8.tar.bz2 |
[mips] Increase the number of floating point control registers available to 32.
Create a dedicated register class for floating point condition code registers and
move FCC0 from register class CCR to the new register class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185373 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/Target/Mips/MipsRegisterInfo.td | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td index 3687084..a5320bb 100644 --- a/lib/Target/Mips/MipsRegisterInfo.td +++ b/lib/Target/Mips/MipsRegisterInfo.td @@ -248,8 +248,9 @@ let Namespace = "Mips" in { def LO64 : RegisterWithSubRegs<"lo", [LO]>; } - // Status flags register - def FCR31 : Register<"31">; + // FP control registers. + foreach I = 0-31 in + def FCR#I : MipsReg<#I, ""#I>; // fcc0 register def FCC0 : MipsReg<0, "fcc0">; @@ -357,8 +358,12 @@ def AFGR64 : RegisterClass<"Mips", [f64], 64, (add def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>; -// Condition Register for floating point operations -def CCR : RegisterClass<"Mips", [i32], 32, (add FCR31,FCC0)>, Unallocatable; +// FP control registers. +def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>, + Unallocatable; + +// FP condition code registers. +def FCC : RegisterClass<"Mips", [i32], 32, (add FCC0)>, Unallocatable; // Hi/Lo Registers def LORegs : RegisterClass<"Mips", [i32], 32, (add LO)>; |