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| author | Daniel Dunbar <daniel@zuster.org> | 2010-03-09 22:50:46 +0000 |
|---|---|---|
| committer | Daniel Dunbar <daniel@zuster.org> | 2010-03-09 22:50:46 +0000 |
| commit | dbde6db26dd437d9b9d76b1a15d84307d4bd5fd6 (patch) | |
| tree | 09d997160df421b1240ff87ff76ecfde1e9de26e /lib | |
| parent | 892e6312efc151d3f66740a03b10803cd2f3ed9b (diff) | |
| download | external_llvm-dbde6db26dd437d9b9d76b1a15d84307d4bd5fd6.zip external_llvm-dbde6db26dd437d9b9d76b1a15d84307d4bd5fd6.tar.gz external_llvm-dbde6db26dd437d9b9d76b1a15d84307d4bd5fd6.tar.bz2 | |
MC/X86: Rename alternate spellings of ADD{8,16,32} and mark as "code gen only" so they don't get selected by the asm matcher.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98098 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/X86/X86InstrInfo.td | 20 |
1 files changed, 11 insertions, 9 deletions
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index 4b43e65..071c5aa 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -2647,6 +2647,17 @@ def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), } // end isConvertibleToThreeAddress } // end isCommutable +// These are alternate spellings for use by the disassembler, we mark them as +// code gen only to ensure they aren't matched by the assembler. +let isCodeGenOnly = 1 in { + def ADD8rr_alt: I<0x02, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), + "add{b}\t{$src2, $dst|$dst, $src2}", []>; + def ADD16rr_alt: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2), + "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize; + def ADD32rr_alt: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2), + "add{l}\t{$src2, $dst|$dst, $src2}", []>; +} + // Register-Memory Addition def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2), @@ -2664,15 +2675,6 @@ def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), [(set GR32:$dst, (add GR32:$src1, (load addr:$src2))), (implicit EFLAGS)]>; -// Register-Register Addition - Equivalent to the normal rr forms (ADD8rr, -// ADD16rr, and ADD32rr), but differently encoded. -def ADD8mrmrr: I<0x02, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), - "add{b}\t{$src2, $dst|$dst, $src2}", []>; -def ADD16mrmrr: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2), - "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize; -def ADD32mrmrr: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2), - "add{l}\t{$src2, $dst|$dst, $src2}", []>; - // Register-Integer Addition def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), "add{b}\t{$src2, $dst|$dst, $src2}", |