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author | Dale Johannesen <dalej@apple.com> | 2009-02-06 21:50:26 +0000 |
---|---|---|
committer | Dale Johannesen <dalej@apple.com> | 2009-02-06 21:50:26 +0000 |
commit | de06470330260f5937e7ca558f5f5b3e171f2ee5 (patch) | |
tree | 926840c1f94d37f5ffe9d3c8b4a8206af82af67e /lib | |
parent | ac06d004a0ac856a747e612708ad4541b18aa165 (diff) | |
download | external_llvm-de06470330260f5937e7ca558f5f5b3e171f2ee5.zip external_llvm-de06470330260f5937e7ca558f5f5b3e171f2ee5.tar.gz external_llvm-de06470330260f5937e7ca558f5f5b3e171f2ee5.tar.bz2 |
Remove more non-DebugLoc versions of getNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63969 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 3 | ||||
-rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp | 4 | ||||
-rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp | 2 | ||||
-rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 22 | ||||
-rw-r--r-- | lib/CodeGen/SelectionDAG/TargetLowering.cpp | 7 | ||||
-rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 94 | ||||
-rw-r--r-- | lib/Target/Alpha/AlphaISelLowering.cpp | 39 | ||||
-rw-r--r-- | lib/Target/CellSPU/SPUISelLowering.cpp | 86 | ||||
-rw-r--r-- | lib/Target/Mips/MipsISelLowering.cpp | 34 | ||||
-rw-r--r-- | lib/Target/PIC16/PIC16ISelLowering.cpp | 49 | ||||
-rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.cpp | 67 | ||||
-rw-r--r-- | lib/Target/Sparc/SparcISelLowering.cpp | 16 | ||||
-rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 12 | ||||
-rw-r--r-- | lib/Target/XCore/XCoreISelLowering.cpp | 19 |
14 files changed, 251 insertions, 203 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index ebe4710..dca3498 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -4075,7 +4075,8 @@ SDValue DAGCombiner::visitFMUL(SDNode *N) { if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), - DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1)); + DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, + N0.getOperand(1), N1)); return SDValue(); } diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp index d29b4df..92b7b30 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -1110,7 +1110,7 @@ void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt, Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(NVTBits-1, ShTy)); } else { - Lo = DAG.getNode(ISD::OR, NVT, + Lo = DAG.getNode(ISD::OR, dl, NVT, DAG.getNode(ISD::SRL, dl, NVT, InL, DAG.getConstant(Amt, ShTy)), DAG.getNode(ISD::SHL, dl, NVT, InH, @@ -2205,7 +2205,7 @@ SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) { DAG.getConstant(NVT.getSizeInBits() - ExcessBits, TLI.getPointerTy())); Hi = DAG.getNode(ISD::OR, dl, NVT, Hi, - DAG.getNode(ISD::SRL, NVT, Lo, + DAG.getNode(ISD::SRL, dl, NVT, Lo, DAG.getConstant(ExcessBits, TLI.getPointerTy()))); } diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp b/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp index ed4a891..ced2e1f 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp @@ -154,7 +154,7 @@ void DAGTypeLegalizer::ExpandRes_EXTRACT_VECTOR_ELT(SDNode *N, SDValue &Lo, if (Idx.getValueType().bitsLT(TLI.getPointerTy())) Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx); - Idx = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, Idx); + Idx = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, Idx); Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); Idx = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 581bdef..5985614 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -2428,11 +2428,6 @@ SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, return SDValue(); } -SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, - SDValue N1, SDValue N2) { - return getNode(Opcode, DebugLoc::getUnknownLoc(), VT, N1, N2); -} - SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, SDValue N1, SDValue N2) { ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); @@ -2793,11 +2788,6 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, return SDValue(N, 0); } -SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, - SDValue N1, SDValue N2, SDValue N3) { - return getNode(Opcode, DebugLoc::getUnknownLoc(), VT, N1, N2, N3); -} - SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, SDValue N1, SDValue N2, SDValue N3) { // Perform various simplifications. @@ -2879,12 +2869,6 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, return SDValue(N, 0); } -SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, - SDValue N1, SDValue N2, SDValue N3, - SDValue N4) { - return getNode(Opcode, DebugLoc::getUnknownLoc(), VT, N1, N2, N3, N4); -} - SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, SDValue N1, SDValue N2, SDValue N3, SDValue N4) { @@ -2892,12 +2876,6 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, return getNode(Opcode, DL, VT, Ops, 4); } -SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, - SDValue N1, SDValue N2, SDValue N3, - SDValue N4, SDValue N5) { - return getNode(Opcode, DebugLoc::getUnknownLoc(), VT, N1, N2, N3, N4, N5); -} - SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, SDValue N1, SDValue N2, SDValue N3, SDValue N4, SDValue N5) { diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 0f7db6e..06fbf2a 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -723,6 +723,7 @@ TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { /// constant and return true. bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, const APInt &Demanded) { + DebugLoc dl = Op.getDebugLoc(); // FIXME: ISD::SELECT, ISD::SELECT_CC switch (Op.getOpcode()) { default: break; @@ -732,7 +733,7 @@ bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) if (C->getAPIntValue().intersects(~Demanded)) { MVT VT = Op.getValueType(); - SDValue New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0), + SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), DAG.getConstant(Demanded & C->getAPIntValue(), VT)); @@ -890,7 +891,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op, // (but not both) turn this into an *inclusive* or. // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 if ((NewMask & ~KnownZero & ~KnownZero2) == 0) - return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, Op.getValueType(), + return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(), Op.getOperand(0), Op.getOperand(1))); @@ -1867,7 +1868,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1, case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y Temp = DAG.getNOT(dl, N0, MVT::i1); - N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp); + N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp); if (!DCI.isCalledByLegalizer()) DCI.AddToWorklist(Temp.getNode()); break; diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 16e2deb..307d464 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -659,18 +659,19 @@ static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) { abort(); case 1: { SDValue LR = DAG.getRegister(ARM::LR, MVT::i32); - return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Chain); + return DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain); } case 3: Op = Op.getOperand(1); if (Op.getValueType() == MVT::f32) { - Op = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); + Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); } else if (Op.getValueType() == MVT::f64) { // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is // available. - Op = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32), &Op,1); + Op = DAG.getNode(ARMISD::FMRRD, dl, + DAG.getVTList(MVT::i32, MVT::i32), &Op,1); SDValue Sign = DAG.getConstant(0, MVT::i32); - return DAG.getNode(ISD::RET, MVT::Other, Chain, Op, Sign, + return DAG.getNode(ISD::RET, dl, MVT::Other, Chain, Op, Sign, Op.getValue(1), Sign); } Copy = DAG.getCopyToReg(Chain, dl, ARM::R0, Op, SDValue()); @@ -707,7 +708,7 @@ static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) { } //We must use RET_FLAG instead of BRIND because BRIND doesn't have a flag - return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); + return DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Copy, Copy.getValue(1)); } // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as @@ -1073,7 +1074,8 @@ static bool isLegalCmpImmediate(unsigned C, bool isThumb) { /// Returns appropriate ARM CMP (cmp) and corresponding condition code for /// the given operands. static SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, - SDValue &ARMCC, SelectionDAG &DAG, bool isThumb) { + SDValue &ARMCC, SelectionDAG &DAG, bool isThumb, + DebugLoc dl) { if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) { unsigned C = RHSC->getZExtValue(); if (!isLegalCmpImmediate(C, isThumb)) { @@ -1127,17 +1129,18 @@ static SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, break; } ARMCC = DAG.getConstant(CondCode, MVT::i32); - return DAG.getNode(CompareType, MVT::Flag, LHS, RHS); + return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS); } /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands. -static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG) { +static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG, + DebugLoc dl) { SDValue Cmp; if (!isFloatingPointZero(RHS)) - Cmp = DAG.getNode(ARMISD::CMPFP, MVT::Flag, LHS, RHS); + Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS); else - Cmp = DAG.getNode(ARMISD::CMPFPw0, MVT::Flag, LHS); - return DAG.getNode(ARMISD::FMSTAT, MVT::Flag, Cmp); + Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS); + return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp); } static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, @@ -1148,12 +1151,13 @@ static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); SDValue TrueVal = Op.getOperand(2); SDValue FalseVal = Op.getOperand(3); + DebugLoc dl = Op.getDebugLoc(); if (LHS.getValueType() == MVT::i32) { SDValue ARMCC; SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); - SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb()); - return DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, ARMCC, CCR, Cmp); + SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb(), dl); + return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, CCR,Cmp); } ARMCC::CondCodes CondCode, CondCode2; @@ -1162,14 +1166,15 @@ static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32); SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); - SDValue Cmp = getVFPCmp(LHS, RHS, DAG); - SDValue Result = DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, + SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl); + SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, CCR, Cmp); if (CondCode2 != ARMCC::AL) { SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32); // FIXME: Needs another CMP because flag can have but one use. - SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG); - Result = DAG.getNode(ARMISD::CMOV, VT, Result, TrueVal, ARMCC2, CCR, Cmp2); + SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl); + Result = DAG.getNode(ARMISD::CMOV, dl, VT, + Result, TrueVal, ARMCC2, CCR, Cmp2); } return Result; } @@ -1181,12 +1186,14 @@ static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG, SDValue LHS = Op.getOperand(2); SDValue RHS = Op.getOperand(3); SDValue Dest = Op.getOperand(4); + DebugLoc dl = Op.getDebugLoc(); if (LHS.getValueType() == MVT::i32) { SDValue ARMCC; SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); - SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb()); - return DAG.getNode(ARMISD::BRCOND, MVT::Other, Chain, Dest, ARMCC, CCR,Cmp); + SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb(), dl); + return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, + Chain, Dest, ARMCC, CCR,Cmp); } assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64); @@ -1195,16 +1202,16 @@ static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG, // Swap the LHS/RHS of the comparison if needed. std::swap(LHS, RHS); - SDValue Cmp = getVFPCmp(LHS, RHS, DAG); + SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl); SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32); SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag); SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp }; - SDValue Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5); + SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5); if (CondCode2 != ARMCC::AL) { ARMCC = DAG.getConstant(CondCode2, MVT::i32); SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) }; - Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5); + Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5); } return Res; } @@ -1220,7 +1227,7 @@ SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) { ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>(); SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy); SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy); - Table = DAG.getNode(ARMISD::WrapperJT, MVT::i32, JTI, UId); + Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId); Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy)); SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); bool isPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; @@ -1233,32 +1240,35 @@ SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) { } static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getDebugLoc(); unsigned Opc = Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI; - Op = DAG.getNode(Opc, MVT::f32, Op.getOperand(0)); - return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); + Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0)); + return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); } static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) { MVT VT = Op.getValueType(); + DebugLoc dl = Op.getDebugLoc(); unsigned Opc = Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF; - Op = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0)); - return DAG.getNode(Opc, VT, Op); + Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0)); + return DAG.getNode(Opc, dl, VT, Op); } static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) { // Implement fcopysign with a fabs and a conditional fneg. SDValue Tmp0 = Op.getOperand(0); SDValue Tmp1 = Op.getOperand(1); + DebugLoc dl = Op.getDebugLoc(); MVT VT = Op.getValueType(); MVT SrcVT = Tmp1.getValueType(); - SDValue AbsVal = DAG.getNode(ISD::FABS, VT, Tmp0); - SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG); + SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0); + SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG, dl); SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32); SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); - return DAG.getNode(ARMISD::CNEG, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp); + return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp); } SDValue @@ -1371,21 +1381,22 @@ ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) { SDValue Op = N->getOperand(0); + DebugLoc dl = N->getDebugLoc(); if (N->getValueType(0) == MVT::f64) { // Turn i64->f64 into FMDRR. - SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op, + SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op, DAG.getConstant(0, MVT::i32)); - SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op, + SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op, DAG.getConstant(1, MVT::i32)); - return DAG.getNode(ARMISD::FMDRR, MVT::f64, Lo, Hi); + return DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi); } // Turn f64->i64 into FMRRD. - SDValue Cvt = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32), - &Op, 1); + SDValue Cvt = DAG.getNode(ARMISD::FMRRD, dl, + DAG.getVTList(MVT::i32, MVT::i32), &Op, 1); // Merge the pieces into a single i64 value. - return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Cvt, Cvt.getValue(1)); + return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1)); } static SDValue ExpandSRx(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) { @@ -1402,21 +1413,22 @@ static SDValue ExpandSRx(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) { if (ST->isThumb()) return SDValue(); // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr. - SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0), + DebugLoc dl = N->getDebugLoc(); + SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), DAG.getConstant(0, MVT::i32)); - SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0), + SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), DAG.getConstant(1, MVT::i32)); // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and // captures the result into a carry flag. unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG; - Hi = DAG.getNode(Opc, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1); + Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1); // The low part is an ARMISD::RRX operand, which shifts the carry in. - Lo = DAG.getNode(ARMISD::RRX, MVT::i32, Lo, Hi.getValue(1)); + Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1)); // Merge the pieces into a single i64 value. - return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); + return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); } diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp index c400ff9..564c779 100644 --- a/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/lib/Target/Alpha/AlphaISelLowering.cpp @@ -186,10 +186,12 @@ static SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) { JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); SDValue Zero = DAG.getConstant(0, PtrVT); + // FIXME there isn't really any debug info here + DebugLoc dl = Op.getDebugLoc(); - SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, JTI, + SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, JTI, DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64)); - SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, JTI, Hi); + SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, JTI, Hi); return Lo; } @@ -482,7 +484,8 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { switch (IntNo) { default: break; // Don't custom lower most intrinsics. case Intrinsic::alpha_umulh: - return DAG.getNode(ISD::MULHU, MVT::i64, Op.getOperand(1), Op.getOperand(2)); + return DAG.getNode(ISD::MULHU, dl, MVT::i64, + Op.getOperand(1), Op.getOperand(2)); } } @@ -491,8 +494,8 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { "Unhandled SINT_TO_FP type in custom expander!"); SDValue LD; bool isDouble = Op.getValueType() == MVT::f64; - LD = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0)); - SDValue FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_, + LD = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op.getOperand(0)); + SDValue FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_, dl, isDouble?MVT::f64:MVT::f32, LD); return FP; } @@ -501,20 +504,21 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { SDValue src = Op.getOperand(0); if (!isDouble) //Promote - src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, src); + src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, src); - src = DAG.getNode(AlphaISD::CVTTQ_, MVT::f64, src); + src = DAG.getNode(AlphaISD::CVTTQ_, dl, MVT::f64, src); - return DAG.getNode(ISD::BIT_CONVERT, MVT::i64, src); + return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, src); } case ISD::ConstantPool: { ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); Constant *C = CP->getConstVal(); SDValue CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment()); + // FIXME there isn't really any debug info here - SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, CPI, + SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, CPI, DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64)); - SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, CPI, Hi); + SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, CPI, Hi); return Lo; } case ISD::GlobalTLSAddress: @@ -523,19 +527,20 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); GlobalValue *GV = GSDN->getGlobal(); SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset()); + // FIXME there isn't really any debug info here // if (!GV->hasWeakLinkage() && !GV->isDeclaration() && !GV->hasLinkOnceLinkage()) { if (GV->hasLocalLinkage()) { - SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA, + SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, GA, DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64)); - SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi); + SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, GA, Hi); return Lo; } else - return DAG.getNode(AlphaISD::RelLit, MVT::i64, GA, + return DAG.getNode(AlphaISD::RelLit, dl, MVT::i64, GA, DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64)); } case ISD::ExternalSymbol: { - return DAG.getNode(AlphaISD::RelLit, MVT::i64, + return DAG.getNode(AlphaISD::RelLit, dl, MVT::i64, DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op) ->getSymbol(), MVT::i64), DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64)); @@ -549,8 +554,8 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { SDValue Tmp1 = Op.getNode()->getOpcode() == ISD::UREM ? BuildUDIV(Op.getNode(), DAG, NULL) : BuildSDIV(Op.getNode(), DAG, NULL); - Tmp1 = DAG.getNode(ISD::MUL, VT, Tmp1, Op.getOperand(1)); - Tmp1 = DAG.getNode(ISD::SUB, VT, Op.getOperand(0), Tmp1); + Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Op.getOperand(1)); + Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Op.getOperand(0), Tmp1); return Tmp1; } //fall through @@ -570,7 +575,7 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { SDValue Tmp1 = Op.getOperand(0), Tmp2 = Op.getOperand(1), Addr = DAG.getExternalSymbol(opstr, MVT::i64); - return DAG.getNode(AlphaISD::DivCall, MVT::i64, Addr, Tmp1, Tmp2); + return DAG.getNode(AlphaISD::DivCall, dl, MVT::i64, Addr, Tmp1, Tmp2); } break; diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp index 14bb8d0..f4c5120 100644 --- a/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/lib/Target/CellSPU/SPUISelLowering.cpp @@ -534,7 +534,7 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { // Simplify the base pointer for this case: basePtr = basePtr.getOperand(0); if ((offset & ~0xf) > 0) { - basePtr = DAG.getNode(SPUISD::IndirectAddr, PtrVT, + basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, basePtr, DAG.getConstant((offset & ~0xf), PtrVT)); } @@ -573,16 +573,16 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { // Convert the (add <ptr>, <const>) to an indirect address contained // in a register. Note that this is done because we need to avoid // creating a 0(reg) d-form address due to the SPU's block loads. - basePtr = DAG.getNode(SPUISD::IndirectAddr, PtrVT, Op0, Op1); + basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Op0, Op1); the_chain = DAG.getCopyToReg(the_chain, dl, VReg, basePtr, Flag); basePtr = DAG.getCopyFromReg(the_chain, dl, VReg, PtrVT); } else { // Convert the (add <arg1>, <arg2>) to an indirect address, which // will likely be lowered as a reg(reg) x-form address. - basePtr = DAG.getNode(SPUISD::IndirectAddr, PtrVT, Op0, Op1); + basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Op0, Op1); } } else { - basePtr = DAG.getNode(SPUISD::IndirectAddr, PtrVT, + basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, basePtr, DAG.getConstant(0, PtrVT)); } @@ -690,18 +690,18 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { // Simplify the base pointer for this case: basePtr = basePtr.getOperand(0); - insertEltOffs = DAG.getNode(SPUISD::IndirectAddr, PtrVT, + insertEltOffs = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, basePtr, DAG.getConstant((offset & 0xf), PtrVT)); if ((offset & ~0xf) > 0) { - basePtr = DAG.getNode(SPUISD::IndirectAddr, PtrVT, + basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, basePtr, DAG.getConstant((offset & ~0xf), PtrVT)); } } else { // Otherwise, assume it's at byte 0 of basePtr - insertEltOffs = DAG.getNode(SPUISD::IndirectAddr, PtrVT, + insertEltOffs = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, basePtr, DAG.getConstant(0, PtrVT)); } @@ -720,16 +720,16 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { // Convert the (add <ptr>, <const>) to an indirect address contained // in a register. Note that this is done because we need to avoid // creating a 0(reg) d-form address due to the SPU's block loads. - basePtr = DAG.getNode(SPUISD::IndirectAddr, PtrVT, Op0, Op1); + basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Op0, Op1); the_chain = DAG.getCopyToReg(the_chain, dl, VReg, basePtr, Flag); basePtr = DAG.getCopyFromReg(the_chain, dl, VReg, PtrVT); } else { // Convert the (add <arg1>, <arg2>) to an indirect address, which // will likely be lowered as a reg(reg) x-form address. - basePtr = DAG.getNode(SPUISD::IndirectAddr, PtrVT, Op0, Op1); + basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Op0, Op1); } } else { - basePtr = DAG.getNode(SPUISD::IndirectAddr, PtrVT, + basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, basePtr, DAG.getConstant(0, PtrVT)); } @@ -825,15 +825,17 @@ LowerConstantPool(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { SDValue CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment()); SDValue Zero = DAG.getConstant(0, PtrVT); const TargetMachine &TM = DAG.getTarget(); + // FIXME there is no actual debug info here + DebugLoc dl = Op.getDebugLoc(); if (TM.getRelocationModel() == Reloc::Static) { if (!ST->usingLargeMem()) { // Just return the SDValue with the constant pool address in it. - return DAG.getNode(SPUISD::AFormAddr, PtrVT, CPI, Zero); + return DAG.getNode(SPUISD::AFormAddr, dl, PtrVT, CPI, Zero); } else { - SDValue Hi = DAG.getNode(SPUISD::Hi, PtrVT, CPI, Zero); - SDValue Lo = DAG.getNode(SPUISD::Lo, PtrVT, CPI, Zero); - return DAG.getNode(SPUISD::IndirectAddr, PtrVT, Hi, Lo); + SDValue Hi = DAG.getNode(SPUISD::Hi, dl, PtrVT, CPI, Zero); + SDValue Lo = DAG.getNode(SPUISD::Lo, dl, PtrVT, CPI, Zero); + return DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Hi, Lo); } } @@ -856,14 +858,16 @@ LowerJumpTable(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); SDValue Zero = DAG.getConstant(0, PtrVT); const TargetMachine &TM = DAG.getTarget(); + // FIXME there is no actual debug info here + DebugLoc dl = Op.getDebugLoc(); if (TM.getRelocationModel() == Reloc::Static) { if (!ST->usingLargeMem()) { - return DAG.getNode(SPUISD::AFormAddr, PtrVT, JTI, Zero); + return DAG.getNode(SPUISD::AFormAddr, dl, PtrVT, JTI, Zero); } else { - SDValue Hi = DAG.getNode(SPUISD::Hi, PtrVT, JTI, Zero); - SDValue Lo = DAG.getNode(SPUISD::Lo, PtrVT, JTI, Zero); - return DAG.getNode(SPUISD::IndirectAddr, PtrVT, Hi, Lo); + SDValue Hi = DAG.getNode(SPUISD::Hi, dl, PtrVT, JTI, Zero); + SDValue Lo = DAG.getNode(SPUISD::Lo, dl, PtrVT, JTI, Zero); + return DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Hi, Lo); } } @@ -880,14 +884,16 @@ LowerGlobalAddress(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { SDValue GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset()); const TargetMachine &TM = DAG.getTarget(); SDValue Zero = DAG.getConstant(0, PtrVT); + // FIXME there is no actual debug info here + DebugLoc dl = Op.getDebugLoc(); if (TM.getRelocationModel() == Reloc::Static) { if (!ST->usingLargeMem()) { - return DAG.getNode(SPUISD::AFormAddr, PtrVT, GA, Zero); + return DAG.getNode(SPUISD::AFormAddr, dl, PtrVT, GA, Zero); } else { - SDValue Hi = DAG.getNode(SPUISD::Hi, PtrVT, GA, Zero); - SDValue Lo = DAG.getNode(SPUISD::Lo, PtrVT, GA, Zero); - return DAG.getNode(SPUISD::IndirectAddr, PtrVT, Hi, Lo); + SDValue Hi = DAG.getNode(SPUISD::Hi, dl, PtrVT, GA, Zero); + SDValue Lo = DAG.getNode(SPUISD::Lo, dl, PtrVT, GA, Zero); + return DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Hi, Lo); } } else { cerr << "LowerGlobalAddress: Relocation model other than static not " @@ -903,6 +909,8 @@ LowerGlobalAddress(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { static SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG) { MVT VT = Op.getValueType(); + // FIXME there is no actual debug info here + DebugLoc dl = Op.getDebugLoc(); if (VT == MVT::f64) { ConstantFPSDNode *FP = cast<ConstantFPSDNode>(Op.getNode()); @@ -912,8 +920,8 @@ LowerConstantFP(SDValue Op, SelectionDAG &DAG) { uint64_t dbits = DoubleToBits(FP->getValueAPF().convertToDouble()); SDValue T = DAG.getConstant(dbits, MVT::i64); - SDValue Tvec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i64, T, T); - return DAG.getNode(SPUISD::VEC2PREFSLOT, VT, + SDValue Tvec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, T, T); + return DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT, DAG.getNode(ISD::BIT_CONVERT, MVT::v2f64, Tvec)); } @@ -1175,14 +1183,14 @@ LowerCALL(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { // This may be an unsafe assumption for JIT and really large compilation // units. if (GV->isDeclaration()) { - Callee = DAG.getNode(SPUISD::AFormAddr, CalleeVT, GA, Zero); + Callee = DAG.getNode(SPUISD::AFormAddr, dl, CalleeVT, GA, Zero); } else { - Callee = DAG.getNode(SPUISD::PCRelAddr, CalleeVT, GA, Zero); + Callee = DAG.getNode(SPUISD::PCRelAddr, dl, CalleeVT, GA, Zero); } } else { // "Large memory" mode: Turn all calls into indirect calls with a X-form // address pairs: - Callee = DAG.getNode(SPUISD::IndirectAddr, PtrVT, GA, Zero); + Callee = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, GA, Zero); } } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { MVT CalleeVT = Callee.getValueType(); @@ -1191,9 +1199,9 @@ LowerCALL(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { Callee.getValueType()); if (!ST->usingLargeMem()) { - Callee = DAG.getNode(SPUISD::AFormAddr, CalleeVT, ExtSym, Zero); + Callee = DAG.getNode(SPUISD::AFormAddr, dl, CalleeVT, ExtSym, Zero); } else { - Callee = DAG.getNode(SPUISD::IndirectAddr, PtrVT, ExtSym, Zero); + Callee = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, ExtSym, Zero); } } else if (SDNode *Dest = isLSAAddress(Callee, DAG)) { // If this is an absolute destination address that appears to be a legal @@ -2619,6 +2627,7 @@ static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, SDValue trueval = Op.getOperand(2); SDValue falseval = Op.getOperand(3); SDValue condition = Op.getOperand(4); + DebugLoc dl = Op.getDebugLoc(); // NOTE: SELB's arguments: $rA, $rB, $mask // @@ -2631,10 +2640,10 @@ static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, // legalizer insists on combining SETCC/SELECT into SELECT_CC, so we end up // with another "cannot select select_cc" assert: - SDValue compare = DAG.getNode(ISD::SETCC, + SDValue compare = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(Op.getValueType()), lhs, rhs, condition); - return DAG.getNode(SPUISD::SELB, VT, falseval, trueval, compare); + return DAG.getNode(SPUISD::SELB, dl, VT, falseval, trueval, compare); } //! Custom lower ISD::TRUNCATE @@ -2643,6 +2652,7 @@ static SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) MVT VT = Op.getValueType(); MVT::SimpleValueType simpleVT = VT.getSimpleVT(); MVT VecVT = MVT::getVectorVT(VT, (128 / VT.getSizeInBits())); + DebugLoc dl = Op.getDebugLoc(); SDValue Op0 = Op.getOperand(0); MVT Op0VT = Op0.getValueType(); @@ -2653,19 +2663,20 @@ static SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) unsigned maskHigh = 0x08090a0b; unsigned maskLow = 0x0c0d0e0f; // Use a shuffle to perform the truncation - SDValue shufMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, + SDValue shufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, DAG.getConstant(maskHigh, MVT::i32), DAG.getConstant(maskLow, MVT::i32), DAG.getConstant(maskHigh, MVT::i32), DAG.getConstant(maskLow, MVT::i32)); - SDValue PromoteScalar = DAG.getNode(SPUISD::PREFSLOT2VEC, Op0VecVT, Op0); + SDValue PromoteScalar = DAG.getNode(SPUISD::PREFSLOT2VEC, dl, + Op0VecVT, Op0); - SDValue truncShuffle = DAG.getNode(SPUISD::SHUFB, Op0VecVT, + SDValue truncShuffle = DAG.getNode(SPUISD::SHUFB, dl, Op0VecVT, PromoteScalar, PromoteScalar, shufMask); - return DAG.getNode(SPUISD::VEC2PREFSLOT, VT, + return DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT, DAG.getNode(ISD::BIT_CONVERT, VecVT, truncShuffle)); } @@ -2812,6 +2823,7 @@ SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const MVT NodeVT = N->getValueType(0); // The node's value type MVT Op0VT = Op0.getValueType(); // The first operand's result SDValue Result; // Initially, empty result + DebugLoc dl = N->getDebugLoc(); switch (N->getOpcode()) { default: break; @@ -2862,7 +2874,7 @@ SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const } #endif - return DAG.getNode(SPUISD::IndirectAddr, Op0VT, + return DAG.getNode(SPUISD::IndirectAddr, dl, Op0VT, IndirectArg, combinedValue); } } @@ -2920,7 +2932,7 @@ SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const } #endif - return DAG.getNode(SPUISD::IndirectAddr, Op0VT, + return DAG.getNode(SPUISD::IndirectAddr, dl, Op0VT, Op0.getOperand(0), Op0.getOperand(1)); } } diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index 42df91f..fe7ece1 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -391,19 +391,20 @@ LowerANDOR(SDValue Op, SelectionDAG &DAG) { SDValue LHS = Op.getOperand(0); SDValue RHS = Op.getOperand(1); - + DebugLoc dl = Op.getDebugLoc(); + if (LHS.getOpcode() != MipsISD::FPCmp || RHS.getOpcode() != MipsISD::FPCmp) return Op; SDValue True = DAG.getConstant(1, MVT::i32); SDValue False = DAG.getConstant(0, MVT::i32); - SDValue LSEL = DAG.getNode(MipsISD::FPSelectCC, True.getValueType(), + SDValue LSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(), LHS, True, False, LHS.getOperand(2)); - SDValue RSEL = DAG.getNode(MipsISD::FPSelectCC, True.getValueType(), + SDValue RSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(), RHS, True, False, RHS.getOperand(2)); - return DAG.getNode(Op.getOpcode(), MVT::i32, LSEL, RSEL); + return DAG.getNode(Op.getOpcode(), dl, MVT::i32, LSEL, RSEL); } SDValue MipsTargetLowering:: @@ -413,6 +414,7 @@ LowerBRCOND(SDValue Op, SelectionDAG &DAG) // the block to branch to if the condition is true. SDValue Chain = Op.getOperand(0); SDValue Dest = Op.getOperand(2); + DebugLoc dl = Op.getDebugLoc(); if (Op.getOperand(1).getOpcode() != MipsISD::FPCmp) return Op; @@ -423,7 +425,7 @@ LowerBRCOND(SDValue Op, SelectionDAG &DAG) (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32); - return DAG.getNode(MipsISD::FPBrcond, Op.getValueType(), Chain, BrCode, + return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode, Dest, CondRes); } @@ -434,11 +436,12 @@ LowerSETCC(SDValue Op, SelectionDAG &DAG) // and #1) and the condition code to compare them with (op #2) as a // CondCodeSDNode. SDValue LHS = Op.getOperand(0); - SDValue RHS = Op.getOperand(1); + SDValue RHS = Op.getOperand(1); + DebugLoc dl = Op.getDebugLoc(); ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); - return DAG.getNode(MipsISD::FPCmp, Op.getValueType(), LHS, RHS, + return DAG.getNode(MipsISD::FPCmp, dl, Op.getValueType(), LHS, RHS, DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32)); } @@ -448,6 +451,7 @@ LowerSELECT(SDValue Op, SelectionDAG &DAG) SDValue Cond = Op.getOperand(0); SDValue True = Op.getOperand(1); SDValue False = Op.getOperand(2); + DebugLoc dl = Op.getDebugLoc(); // if the incomming condition comes from a integer compare, the select // operation must be SelectCC or a conditional move if the subtarget @@ -455,20 +459,21 @@ LowerSELECT(SDValue Op, SelectionDAG &DAG) if (Cond.getOpcode() != MipsISD::FPCmp) { if (Subtarget->hasCondMov() && !True.getValueType().isFloatingPoint()) return Op; - return DAG.getNode(MipsISD::SelectCC, True.getValueType(), + return DAG.getNode(MipsISD::SelectCC, dl, True.getValueType(), Cond, True, False); } // if the incomming condition comes from fpcmp, the select // operation must use FPSelectCC. SDValue CCNode = Cond.getOperand(2); - return DAG.getNode(MipsISD::FPSelectCC, True.getValueType(), + return DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(), Cond, True, False, CCNode); } SDValue MipsTargetLowering:: LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) { + // FIXME there isn't actually debug info here DebugLoc dl = Op.getDebugLoc(); GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32); @@ -478,7 +483,7 @@ LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) SDValue Ops[] = { GA }; // %gp_rel relocation if (!isa<Function>(GV) && IsGlobalInSmallSection(GV)) { - SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, VTs, 1, Ops, 1); + SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, 1, Ops, 1); SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32); return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode); } @@ -514,6 +519,7 @@ LowerJumpTable(SDValue Op, SelectionDAG &DAG) { SDValue ResNode; SDValue HiPart; + // FIXME there isn't actually debug info here DebugLoc dl = Op.getDebugLoc(); MVT PtrVT = Op.getValueType(); @@ -540,6 +546,8 @@ LowerConstantPool(SDValue Op, SelectionDAG &DAG) ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); Constant *C = N->getConstVal(); SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment()); + // FIXME there isn't actually debug info here + DebugLoc dl = Op.getDebugLoc(); // gp_rel relocation // FIXME: we should reference the constant pool using small data sections, @@ -552,9 +560,9 @@ LowerConstantPool(SDValue Op, SelectionDAG &DAG) // SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32); // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode); //} else { // %hi/%lo relocation - SDValue HiPart = DAG.getNode(MipsISD::Hi, MVT::i32, CP); - SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, CP); - ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo); + SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CP); + SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CP); + ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); //} return ResNode; diff --git a/lib/Target/PIC16/PIC16ISelLowering.cpp b/lib/Target/PIC16/PIC16ISelLowering.cpp index 0635c35..28cc082 100644 --- a/lib/Target/PIC16/PIC16ISelLowering.cpp +++ b/lib/Target/PIC16/PIC16ISelLowering.cpp @@ -305,14 +305,16 @@ SDValue PIC16TargetLowering::ExpandFrameIndex(SDNode *N, SelectionDAG &DAG) { MachineFunction &MF = DAG.getMachineFunction(); const Function *Func = MF.getFunction(); const std::string Name = Func->getName(); - + FrameIndexSDNode *FR = dyn_cast<FrameIndexSDNode>(SDValue(N,0)); + // FIXME there isn't really debug info here + DebugLoc dl = FR->getDebugLoc(); int Index = FR->getIndex(); SDValue FI[2]; FI[0] = DAG.getTargetFrameIndex(Index, MVT::i8); FI[1] = DAG.getTargetFrameIndex(Index + 1, MVT::i8); - return DAG.getNode(ISD::BUILD_PAIR, N->getValueType(0), FI[0], FI[1]); + return DAG.getNode(ISD::BUILD_PAIR, dl, N->getValueType(0), FI[0], FI[1]); } @@ -323,12 +325,13 @@ SDValue PIC16TargetLowering::ExpandStore(SDNode *N, SelectionDAG &DAG) { SDValue Ptr = St->getBasePtr(); MVT ValueType = Src.getValueType(); unsigned StoreOffset = 0; + DebugLoc dl = N->getDebugLoc(); SDValue PtrLo, PtrHi; LegalizeAddress(Ptr, DAG, PtrLo, PtrHi, StoreOffset); if (ValueType == MVT::i8) { - return DAG.getNode (PIC16ISD::PIC16Store, MVT::Other, Chain, Src, + return DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other, Chain, Src, PtrLo, PtrHi, DAG.getConstant (0 + StoreOffset, MVT::i8)); } @@ -341,16 +344,16 @@ SDValue PIC16TargetLowering::ExpandStore(SDNode *N, SelectionDAG &DAG) { ChainLo = Chain.getOperand(0); ChainHi = Chain.getOperand(1); } - SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, MVT::Other, + SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainLo, SrcLo, PtrLo, PtrHi, DAG.getConstant (0 + StoreOffset, MVT::i8)); - SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, MVT::Other, ChainHi, + SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi, SrcHi, PtrLo, PtrHi, DAG.getConstant (1 + StoreOffset, MVT::i8)); - return DAG.getNode(ISD::TokenFactor, MVT::Other, getChain(Store1), + return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, getChain(Store1), getChain(Store2)); } else if (ValueType == MVT::i32) { @@ -378,28 +381,28 @@ SDValue PIC16TargetLowering::ExpandStore(SDNode *N, SelectionDAG &DAG) { ChainHi1 = ChainHi.getOperand(0); ChainHi2 = ChainHi.getOperand(1); } - SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, MVT::Other, + SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainLo1, SrcLo1, PtrLo, PtrHi, DAG.getConstant (0 + StoreOffset, MVT::i8)); - SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, MVT::Other, ChainLo2, + SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainLo2, SrcLo2, PtrLo, PtrHi, DAG.getConstant (1 + StoreOffset, MVT::i8)); - SDValue Store3 = DAG.getNode(PIC16ISD::PIC16Store, MVT::Other, ChainHi1, + SDValue Store3 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi1, SrcHi1, PtrLo, PtrHi, DAG.getConstant (2 + StoreOffset, MVT::i8)); - SDValue Store4 = DAG.getNode(PIC16ISD::PIC16Store, MVT::Other, ChainHi2, + SDValue Store4 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi2, SrcHi2, PtrLo, PtrHi, DAG.getConstant (3 + StoreOffset, MVT::i8)); - SDValue RetLo = DAG.getNode(ISD::TokenFactor, MVT::Other, getChain(Store1), - getChain(Store2)); - SDValue RetHi = DAG.getNode(ISD::TokenFactor, MVT::Other, getChain(Store3), - getChain(Store4)); - return DAG.getNode(ISD::TokenFactor, MVT::Other, RetLo, RetHi); + SDValue RetLo = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + getChain(Store1), getChain(Store2)); + SDValue RetHi = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + getChain(Store3), getChain(Store4)); + return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, RetLo, RetHi); } else { @@ -411,26 +414,30 @@ SDValue PIC16TargetLowering::ExpandStore(SDNode *N, SelectionDAG &DAG) { SDValue PIC16TargetLowering::ExpandExternalSymbol(SDNode *N, SelectionDAG &DAG) { ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(SDValue(N, 0)); + // FIXME there isn't really debug info here + DebugLoc dl = ES->getDebugLoc(); SDValue TES = DAG.getTargetExternalSymbol(ES->getSymbol(), MVT::i8); - SDValue Lo = DAG.getNode(PIC16ISD::Lo, MVT::i8, TES); - SDValue Hi = DAG.getNode(PIC16ISD::Hi, MVT::i8, TES); + SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, TES); + SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, TES); - return DAG.getNode(ISD::BUILD_PAIR, MVT::i16, Lo, Hi); + return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16, Lo, Hi); } // ExpandGlobalAddress - SDValue PIC16TargetLowering::ExpandGlobalAddress(SDNode *N, SelectionDAG &DAG) { GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(SDValue(N, 0)); + // FIXME there isn't really debug info here + DebugLoc dl = G->getDebugLoc(); SDValue TGA = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i8, G->getOffset()); - SDValue Lo = DAG.getNode(PIC16ISD::Lo, MVT::i8, TGA); - SDValue Hi = DAG.getNode(PIC16ISD::Hi, MVT::i8, TGA); + SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, TGA); + SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, TGA); - return DAG.getNode(ISD::BUILD_PAIR, MVT::i16, Lo, Hi); + return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16, Lo, Hi); } bool PIC16TargetLowering::isDirectAddress(const SDValue &Op) { diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 3d6b11b..53bce15 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -1075,11 +1075,13 @@ SDValue PPCTargetLowering::LowerConstantPool(SDValue Op, Constant *C = CP->getConstVal(); SDValue CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment()); SDValue Zero = DAG.getConstant(0, PtrVT); + // FIXME there isn't really any debug info here + DebugLoc dl = Op.getDebugLoc(); const TargetMachine &TM = DAG.getTarget(); - SDValue Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero); - SDValue Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero); + SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, CPI, Zero); + SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, CPI, Zero); // If this is a non-darwin platform, we don't support non-static relo models // yet. @@ -1087,16 +1089,16 @@ SDValue PPCTargetLowering::LowerConstantPool(SDValue Op, !TM.getSubtarget<PPCSubtarget>().isDarwin()) { // Generate non-pic code that has direct accesses to the constant pool. // The address of the global is just (hi(&g)+lo(&g)). - return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); + return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); } if (TM.getRelocationModel() == Reloc::PIC_) { // With PIC, the first instruction is actually "GR+hi(&G)". - Hi = DAG.getNode(ISD::ADD, PtrVT, + Hi = DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); } - Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); + Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); return Lo; } @@ -1105,11 +1107,13 @@ SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) { JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); SDValue Zero = DAG.getConstant(0, PtrVT); + // FIXME there isn't really any debug loc here + DebugLoc dl = Op.getDebugLoc(); const TargetMachine &TM = DAG.getTarget(); - SDValue Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero); - SDValue Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero); + SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, JTI, Zero); + SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, JTI, Zero); // If this is a non-darwin platform, we don't support non-static relo models // yet. @@ -1117,16 +1121,16 @@ SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) { !TM.getSubtarget<PPCSubtarget>().isDarwin()) { // Generate non-pic code that has direct accesses to the constant pool. // The address of the global is just (hi(&g)+lo(&g)). - return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); + return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); } if (TM.getRelocationModel() == Reloc::PIC_) { // With PIC, the first instruction is actually "GR+hi(&G)". - Hi = DAG.getNode(ISD::ADD, PtrVT, + Hi = DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); } - Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); + Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); return Lo; } @@ -1143,6 +1147,7 @@ SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op, GlobalValue *GV = GSDN->getGlobal(); SDValue GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset()); SDValue Zero = DAG.getConstant(0, PtrVT); + // FIXME there isn't really any debug info here DebugLoc dl = GSDN->getDebugLoc(); const TargetMachine &TM = DAG.getTarget(); @@ -2771,18 +2776,19 @@ SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, // Get the inputs. SDValue Chain = Op.getOperand(0); SDValue Size = Op.getOperand(1); - + DebugLoc dl = Op.getDebugLoc(); + // Get the corect type for pointers. MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); // Negate the size. - SDValue NegSize = DAG.getNode(ISD::SUB, PtrVT, + SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT, DAG.getConstant(0, PtrVT), Size); // Construct a node for the frame pointer save index. SDValue FPSIdx = getFramePointerFrameIndex(DAG); // Build a DYNALLOC node. SDValue Ops[3] = { Chain, NegSize, FPSIdx }; SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other); - return DAG.getNode(PPCISD::DYNALLOC, VTs, Ops, 3); + return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3); } /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when @@ -2802,6 +2808,7 @@ SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { MVT CmpVT = Op.getOperand(0).getValueType(); SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); SDValue TV = Op.getOperand(2), FV = Op.getOperand(3); + DebugLoc dl = Op.getDebugLoc(); // If the RHS of the comparison is a 0.0, we don't need to do the // subtraction at all. @@ -2814,17 +2821,17 @@ SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { case ISD::SETOGE: case ISD::SETGE: if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits - LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); - return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV); + LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); + return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); case ISD::SETUGT: case ISD::SETGT: std::swap(TV, FV); // fsel is natively setge, swap operands for setlt case ISD::SETOLE: case ISD::SETLE: if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits - LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); - return DAG.getNode(PPCISD::FSEL, ResVT, - DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV); + LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); + return DAG.getNode(PPCISD::FSEL, dl, ResVT, + DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV); } SDValue Cmp; @@ -2832,28 +2839,28 @@ SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { default: break; // SETUO etc aren't handled by fsel. case ISD::SETULT: case ISD::SETLT: - Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); + Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS); if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits - Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); - return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); + Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); + return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); case ISD::SETOGE: case ISD::SETGE: - Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); + Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS); if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits - Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); - return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); + Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); + return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); case ISD::SETUGT: case ISD::SETGT: - Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); + Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS); if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits - Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); - return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); + Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); + return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); case ISD::SETOLE: case ISD::SETLE: - Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); + Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS); if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits - Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); - return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); + Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); + return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); } return SDValue(); } diff --git a/lib/Target/Sparc/SparcISelLowering.cpp b/lib/Target/Sparc/SparcISelLowering.cpp index 479835e..e134e42 100644 --- a/lib/Target/Sparc/SparcISelLowering.cpp +++ b/lib/Target/Sparc/SparcISelLowering.cpp @@ -736,19 +736,23 @@ static void LookThroughSetCC(SDValue &LHS, SDValue &RHS, static SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) { GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); + // FIXME there isn't really any debug info here + DebugLoc dl = Op.getDebugLoc(); SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32); - SDValue Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA); - SDValue Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA); - return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); + SDValue Hi = DAG.getNode(SPISD::Hi, dl, MVT::i32, GA); + SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, GA); + return DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi); } static SDValue LowerCONSTANTPOOL(SDValue Op, SelectionDAG &DAG) { ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); + // FIXME there isn't really any debug info here + DebugLoc dl = Op.getDebugLoc(); Constant *C = N->getConstVal(); SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment()); - SDValue Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP); - SDValue Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP); - return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); + SDValue Hi = DAG.getNode(SPISD::Hi, dl, MVT::i32, CP); + SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, CP); + return DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi); } static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) { diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index e465cf3..9e1ed80 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -4511,6 +4511,8 @@ X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) { SDValue X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) { ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); + // FIXME there isn't really any debug info here, should come from the parent + DebugLoc dl = CP->getDebugLoc(); SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), CP->getAlignment()); @@ -4518,7 +4520,7 @@ X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) { // With PIC, the address is actually $g + Offset. if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && !Subtarget->isPICStyleRIPRel()) { - Result = DAG.getNode(ISD::ADD, getPointerTy(), + Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), Result); } @@ -4693,13 +4695,15 @@ X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) { SDValue X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) { + // FIXME there isn't really any debug info here + DebugLoc dl = Op.getDebugLoc(); const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy()); Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result); // With PIC, the address is actually $g + Offset. if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && !Subtarget->isPICStyleRIPRel()) { - Result = DAG.getNode(ISD::ADD, getPointerTy(), + Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), Result); } @@ -4709,12 +4713,14 @@ X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) { SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) { JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); + // FIXME there isn't really any debug into here + DebugLoc dl = JT->getDebugLoc(); SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy()); Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result); // With PIC, the address is actually $g + Offset. if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && !Subtarget->isPICStyleRIPRel()) { - Result = DAG.getNode(ISD::ADD, getPointerTy(), + Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), Result); } diff --git a/lib/Target/XCore/XCoreISelLowering.cpp b/lib/Target/XCore/XCoreISelLowering.cpp index cd2d93e..87f7199 100644 --- a/lib/Target/XCore/XCoreISelLowering.cpp +++ b/lib/Target/XCore/XCoreISelLowering.cpp @@ -194,9 +194,10 @@ void XCoreTargetLowering::ReplaceNodeResults(SDNode *N, SDValue XCoreTargetLowering:: LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { - SDValue Cond = DAG.getNode(ISD::SETCC, MVT::i32, Op.getOperand(2), + DebugLoc dl = Op.getDebugLoc(); + SDValue Cond = DAG.getNode(ISD::SETCC, dl, MVT::i32, Op.getOperand(2), Op.getOperand(3), Op.getOperand(4)); - return DAG.getNode(ISD::SELECT, MVT::i32, Cond, Op.getOperand(0), + return DAG.getNode(ISD::SELECT, dl, MVT::i32, Cond, Op.getOperand(0), Op.getOperand(1)); } @@ -244,6 +245,8 @@ static inline bool isZeroLengthArray(const Type *Ty) { SDValue XCoreTargetLowering:: LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) { + // FIXME there isn't really debug info here + DebugLoc dl = Op.getDebugLoc(); // transform to label + getid() * size GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32); @@ -266,15 +269,17 @@ LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) SDValue base = getGlobalAddressWrapper(GA, GV, DAG); const TargetData *TD = TM.getTargetData(); unsigned Size = TD->getTypePaddedSize(Ty); - SDValue offset = DAG.getNode(ISD::MUL, MVT::i32, BuildGetId(DAG), + SDValue offset = DAG.getNode(ISD::MUL, dl, MVT::i32, BuildGetId(DAG), DAG.getConstant(Size, MVT::i32)); - return DAG.getNode(ISD::ADD, MVT::i32, base, offset); + return DAG.getNode(ISD::ADD, dl, MVT::i32, base, offset); } SDValue XCoreTargetLowering:: LowerConstantPool(SDValue Op, SelectionDAG &DAG) { ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); + // FIXME there isn't really debug info here + DebugLoc dl = CP->getDebugLoc(); if (Subtarget.isXS1A()) { assert(0 && "Lowering of constant pool unimplemented"); return SDValue(); @@ -288,17 +293,19 @@ LowerConstantPool(SDValue Op, SelectionDAG &DAG) Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment()); } - return DAG.getNode(XCoreISD::CPRelativeWrapper, MVT::i32, Res); + return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, Res); } } SDValue XCoreTargetLowering:: LowerJumpTable(SDValue Op, SelectionDAG &DAG) { + // FIXME there isn't really debug info here + DebugLoc dl = Op.getDebugLoc(); MVT PtrVT = Op.getValueType(); JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); - return DAG.getNode(XCoreISD::DPRelativeWrapper, MVT::i32, JTI); + return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, JTI); } SDValue XCoreTargetLowering:: |