diff options
| author | Arnold Schwaighofer <aschwaighofer@apple.com> | 2013-06-06 17:26:12 +0000 |
|---|---|---|
| committer | Arnold Schwaighofer <aschwaighofer@apple.com> | 2013-06-06 17:26:12 +0000 |
| commit | e022a6b0f45184726afe0aa48ef04a9af3e94b62 (patch) | |
| tree | 6b23d087d659fb361d9c894a15e5fa425bf66728 /lib | |
| parent | 54154f3bf1ae3d2dfd68cc9474cad061b3338a40 (diff) | |
| download | external_llvm-e022a6b0f45184726afe0aa48ef04a9af3e94b62.zip external_llvm-e022a6b0f45184726afe0aa48ef04a9af3e94b62.tar.gz external_llvm-e022a6b0f45184726afe0aa48ef04a9af3e94b62.tar.bz2 | |
ARM sched model: Add preload instructions
Reapply 183261.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183425 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 04d7140..34a5dc1 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -1780,7 +1780,8 @@ multiclass APreLoad<bits<1> read, bits<1> data, string opc> { def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload, !strconcat(opc, "\t$addr"), - [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> { + [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>, + Sched<[WritePreLd]> { bits<4> Rt; bits<17> addr; let Inst{31-26} = 0b111101; @@ -1796,7 +1797,8 @@ multiclass APreLoad<bits<1> read, bits<1> data, string opc> { def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload, !strconcat(opc, "\t$shift"), - [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> { + [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>, + Sched<[WritePreLd]> { bits<17> shift; let Inst{31-26} = 0b111101; let Inst{25} = 1; // 1 for register form |