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| author | Evan Cheng <evan.cheng@apple.com> | 2007-10-05 01:33:45 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2007-10-05 01:33:45 +0000 |
| commit | e203ae9971a0138c06a53b71dbea2bf62311c083 (patch) | |
| tree | e5b61b5b82453736f76db447bb1da97459e8d116 /lib | |
| parent | 66f0f640820b61cf9db814b6d187bae9faf7279c (diff) | |
| download | external_llvm-e203ae9971a0138c06a53b71dbea2bf62311c083.zip external_llvm-e203ae9971a0138c06a53b71dbea2bf62311c083.tar.gz external_llvm-e203ae9971a0138c06a53b71dbea2bf62311c083.tar.bz2 | |
Forgot these.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42622 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/IA64/IA64RegisterInfo.cpp | 62 | ||||
| -rw-r--r-- | lib/Target/IA64/IA64RegisterInfo.h | 10 |
2 files changed, 72 insertions, 0 deletions
diff --git a/lib/Target/IA64/IA64RegisterInfo.cpp b/lib/Target/IA64/IA64RegisterInfo.cpp index 15a0d4a..4c944ad 100644 --- a/lib/Target/IA64/IA64RegisterInfo.cpp +++ b/lib/Target/IA64/IA64RegisterInfo.cpp @@ -60,6 +60,38 @@ void IA64RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, "sorry, I don't know how to store this sort of reg in the stack\n"); } +void IA64RegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, + SmallVector<MachineOperand,4> Addr, + const TargetRegisterClass *RC, + SmallVector<MachineInstr*, 4> &NewMIs) const { + unsigned Opc = 0; + if (RC == IA64::FPRegisterClass) { + Opc = IA64::STF8; + } else if (RC == IA64::GRRegisterClass) { + Opc = IA64::ST8; + } else if (RC == IA64::PRRegisterClass) { + Opc = IA64::ST1; + } else { + assert(0 && + "sorry, I don't know how to store this sort of reg\n"); + } + + MachineInstrBuilder MIB = BuildMI(TII.get(Opc)); + for (unsigned i = 0, e = Addr.size(); i != e; ++i) { + MachineOperand &MO = Addr[i]; + if (MO.isRegister()) + MIB.addReg(MO.getReg()); + else if (MO.isImmediate()) + MIB.addImm(MO.getImmedValue()); + else + MIB.addFrameIndex(MO.getFrameIndex()); + } + MIB.addReg(SrcReg, false, false, true); + NewMIs.push_back(MIB); + return; + +} + void IA64RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, @@ -80,6 +112,36 @@ void IA64RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, "sorry, I don't know how to load this sort of reg from the stack\n"); } +void IA64RegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, + SmallVector<MachineOperand,4> Addr, + const TargetRegisterClass *RC, + SmallVector<MachineInstr*, 4> &NewMIs) const { + unsigned Opc = 0; + if (RC == IA64::FPRegisterClass) { + Opc = IA64::LDF8; + } else if (RC == IA64::GRRegisterClass) { + Opc = IA64::LD8; + } else if (RC == IA64::PRRegisterClass) { + Opc = IA64::LD1; + } else { + assert(0 && + "sorry, I don't know how to store this sort of reg\n"); + } + + MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg); + for (unsigned i = 0, e = Addr.size(); i != e; ++i) { + MachineOperand &MO = Addr[i]; + if (MO.isRegister()) + MIB.addReg(MO.getReg()); + else if (MO.isImmediate()) + MIB.addImm(MO.getImmedValue()); + else + MIB.addFrameIndex(MO.getFrameIndex()); + } + NewMIs.push_back(MIB); + return; +} + void IA64RegisterInfo::copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SrcReg, diff --git a/lib/Target/IA64/IA64RegisterInfo.h b/lib/Target/IA64/IA64RegisterInfo.h index 52e8ed3..c556752 100644 --- a/lib/Target/IA64/IA64RegisterInfo.h +++ b/lib/Target/IA64/IA64RegisterInfo.h @@ -34,11 +34,21 @@ struct IA64RegisterInfo : public IA64GenRegisterInfo { unsigned SrcReg, int FrameIndex, const TargetRegisterClass *RC) const; + void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, + SmallVector<MachineOperand,4> Addr, + const TargetRegisterClass *RC, + SmallVector<MachineInstr*, 4> &NewMIs) const; + void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC) const; + void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, + SmallVector<MachineOperand,4> Addr, + const TargetRegisterClass *RC, + SmallVector<MachineInstr*, 4> &NewMIs) const; + void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SrcReg, |