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author | Evan Cheng <evan.cheng@apple.com> | 2008-03-27 01:41:09 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2008-03-27 01:41:09 +0000 |
commit | e771ebd7a32e760a1eb92ec50513c02d14a996df (patch) | |
tree | cf899207228823df64c3892247eaa26dcf3ae133 /lib | |
parent | d1e4b3515ccc33e45a74fa8fb300f4ff90e67a85 (diff) | |
download | external_llvm-e771ebd7a32e760a1eb92ec50513c02d14a996df.zip external_llvm-e771ebd7a32e760a1eb92ec50513c02d14a996df.tar.gz external_llvm-e771ebd7a32e760a1eb92ec50513c02d14a996df.tar.bz2 |
Allow certain lea instructions to be rematerialized.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48855 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/Target/X86/X86Instr64bit.td | 1 | ||||
-rw-r--r-- | lib/Target/X86/X86InstrInfo.cpp | 101 | ||||
-rw-r--r-- | lib/Target/X86/X86InstrInfo.td | 1 |
3 files changed, 68 insertions, 35 deletions
diff --git a/lib/Target/X86/X86Instr64bit.td b/lib/Target/X86/X86Instr64bit.td index 2dd2d32..effb305 100644 --- a/lib/Target/X86/X86Instr64bit.td +++ b/lib/Target/X86/X86Instr64bit.td @@ -154,6 +154,7 @@ def LEA64_32r : I<0x8D, MRMSrcMem, "lea{l}\t{$src|$dst}, {$dst|$src}", [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>; +let isReMaterializable = 1 in def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src), "lea{q}\t{$src|$dst}, {$dst|$src}", [(set GR64:$dst, lea64addr:$src)]>; diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index 8625300..07c0f4e 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -734,46 +734,77 @@ unsigned X86InstrInfo::isStoreToStackSlot(MachineInstr *MI, } + static bool regIsPICBase(MachineInstr *MI, unsigned BaseReg) { + MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); + bool isPICBase = false; + for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg), + E = MRI.def_end(); I != E; ++I) { + MachineInstr *DefMI = I.getOperand().getParent(); + if (DefMI->getOpcode() != X86::MOVPC32r) + return false; + assert(!isPICBase && "More than one PIC base?"); + isPICBase = true; + } + return isPICBase; + } + bool X86InstrInfo::isReallyTriviallyReMaterializable(MachineInstr *MI) const { switch (MI->getOpcode()) { default: break; - case X86::MOV8rm: - case X86::MOV16rm: - case X86::MOV16_rm: - case X86::MOV32rm: - case X86::MOV32_rm: - case X86::MOV64rm: - case X86::LD_Fp64m: - case X86::MOVSSrm: - case X86::MOVSDrm: - case X86::MOVAPSrm: - case X86::MOVAPDrm: - case X86::MMX_MOVD64rm: - case X86::MMX_MOVQ64rm: - // Loads from constant pools are trivially rematerializable. - if (MI->getOperand(1).isReg() && MI->getOperand(2).isImm() && - MI->getOperand(3).isReg() && MI->getOperand(4).isCPI() && - MI->getOperand(2).getImm() == 1 && - MI->getOperand(3).getReg() == 0) { - unsigned BaseReg = MI->getOperand(1).getReg(); - if (BaseReg == 0) - return true; - // Allow re-materialization of PIC load. - MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); - bool isPICBase = false; - for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg), - E = MRI.def_end(); I != E; ++I) { - MachineInstr *DefMI = I.getOperand().getParent(); - if (DefMI->getOpcode() != X86::MOVPC32r) - return false; - assert(!isPICBase && "More than one PIC base?"); - isPICBase = true; - } - return isPICBase; + case X86::MOV8rm: + case X86::MOV16rm: + case X86::MOV16_rm: + case X86::MOV32rm: + case X86::MOV32_rm: + case X86::MOV64rm: + case X86::LD_Fp64m: + case X86::MOVSSrm: + case X86::MOVSDrm: + case X86::MOVAPSrm: + case X86::MOVAPDrm: + case X86::MMX_MOVD64rm: + case X86::MMX_MOVQ64rm: { + // Loads from constant pools are trivially rematerializable. + if (MI->getOperand(1).isReg() && + MI->getOperand(2).isImm() && + MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 && + MI->getOperand(4).isCPI()) { + unsigned BaseReg = MI->getOperand(1).getReg(); + if (BaseReg == 0) + return true; + // Allow re-materialization of PIC load. + MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); + bool isPICBase = false; + for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg), + E = MRI.def_end(); I != E; ++I) { + MachineInstr *DefMI = I.getOperand().getParent(); + if (DefMI->getOpcode() != X86::MOVPC32r) + return false; + assert(!isPICBase && "More than one PIC base?"); + isPICBase = true; + } + return isPICBase; + } + return false; } - - return false; + + case X86::LEA32r: + case X86::LEA64r: { + if (MI->getOperand(1).isReg() && + MI->getOperand(2).isImm() && + MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 && + !MI->getOperand(4).isReg()) { + // lea fi#, lea GV, etc. are all rematerializable. + unsigned BaseReg = MI->getOperand(1).getReg(); + if (BaseReg == 0) + return true; + // Allow re-materialization of lea PICBase + x. + return regIsPICBase(MI, BaseReg); + } + return false; + } } + // All other instructions marked M_REMATERIALIZABLE are always trivially // rematerializable. return true; diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index 006d7a0..3141af3 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -464,6 +464,7 @@ let neverHasSideEffects = 1 in def LEA16r : I<0x8D, MRMSrcMem, (outs GR16:$dst), (ins i32mem:$src), "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize; +let isReMaterializable = 1 in def LEA32r : I<0x8D, MRMSrcMem, (outs GR32:$dst), (ins lea32mem:$src), "lea{l}\t{$src|$dst}, {$dst|$src}", |