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| author | Chris Lattner <sabre@nondot.org> | 2010-03-19 04:53:47 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2010-03-19 04:53:47 +0000 |
| commit | e9eda0f85d8727b2f109d42752cd7f1bf6ef95e0 (patch) | |
| tree | f11281b7c5185e4fe09cb06a8f89d149237a7d78 /lib | |
| parent | 2356ae91797eb06ab2612bfc66a810b4a1826cf4 (diff) | |
| download | external_llvm-e9eda0f85d8727b2f109d42752cd7f1bf6ef95e0.zip external_llvm-e9eda0f85d8727b2f109d42752cd7f1bf6ef95e0.tar.gz external_llvm-e9eda0f85d8727b2f109d42752cd7f1bf6ef95e0.tar.bz2 | |
remove some damaged sign extend patterns that can never match.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98932 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/CellSPU/SPUInstrInfo.td | 14 |
1 files changed, 6 insertions, 8 deletions
diff --git a/lib/Target/CellSPU/SPUInstrInfo.td b/lib/Target/CellSPU/SPUInstrInfo.td index ad12604..5068f77 100644 --- a/lib/Target/CellSPU/SPUInstrInfo.td +++ b/lib/Target/CellSPU/SPUInstrInfo.td @@ -1133,16 +1133,14 @@ class XSBHInst<dag OOL, dag IOL, list<dag> pattern>: "xsbh\t$rDst, $rSrc", IntegerOp, pattern>; -class XSBHVecInst<ValueType vectype>: - XSBHInst<(outs VECREG:$rDst), (ins VECREG:$rSrc), - [(set (v8i16 VECREG:$rDst), (sext (vectype VECREG:$rSrc)))]>; - class XSBHInRegInst<RegisterClass rclass, list<dag> pattern>: XSBHInst<(outs rclass:$rDst), (ins rclass:$rSrc), pattern>; multiclass ExtendByteHalfword { - def v16i8: XSBHVecInst<v8i16>; + def v16i8: XSBHInst<(outs VECREG:$rDst), (ins VECREG:$rSrc), + [ + /*(set (v8i16 VECREG:$rDst), (sext (v8i16 VECREG:$rSrc)))*/]>; def r8: XSBHInst<(outs R16C:$rDst), (ins R8C:$rSrc), [(set R16C:$rDst, (sext R8C:$rSrc))]>; def r16: XSBHInRegInst<R16C, @@ -1200,8 +1198,8 @@ class XSWDInst<dag OOL, dag IOL, list<dag> pattern>: class XSWDVecInst<ValueType in_vectype, ValueType out_vectype>: XSWDInst<(outs VECREG:$rDst), (ins VECREG:$rSrc), - [(set (out_vectype VECREG:$rDst), - (sext (out_vectype VECREG:$rSrc)))]>; + [/*(set (out_vectype VECREG:$rDst), + (sext (out_vectype VECREG:$rSrc)))*/]>; class XSWDRegInst<RegisterClass in_rclass, RegisterClass out_rclass>: XSWDInst<(outs out_rclass:$rDst), (ins in_rclass:$rSrc), @@ -4146,7 +4144,7 @@ def CFSif32 : def FESDvec : RRForm_1<0b00011101110, (outs VECREG:$rT), (ins VECREG:$rA), "fesd\t$rT, $rA", SPrecFP, - [(set (v2f64 VECREG:$rT), (fextend (v4f32 VECREG:$rA)))]>; + [/*(set (v2f64 VECREG:$rT), (fextend (v4f32 VECREG:$rA)))*/]>; def FESDf32 : RRForm_1<0b00011101110, (outs R64FP:$rT), (ins R32FP:$rA), |