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author | Mon P Wang <wangmp@apple.com> | 2008-12-09 05:46:39 +0000 |
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committer | Mon P Wang <wangmp@apple.com> | 2008-12-09 05:46:39 +0000 |
commit | e9f1015d1f184a51aaadfd03be0846bd5e7d08a2 (patch) | |
tree | f27edc0e889c8e493c2cd58da91ad01fd86cf2d9 /lib | |
parent | 46a879ebd384fb39cb680e4c3c182fefcdef5778 (diff) | |
download | external_llvm-e9f1015d1f184a51aaadfd03be0846bd5e7d08a2.zip external_llvm-e9f1015d1f184a51aaadfd03be0846bd5e7d08a2.tar.gz external_llvm-e9f1015d1f184a51aaadfd03be0846bd5e7d08a2.tar.bz2 |
Fix getNode to allow a vector for the shift amount for shifts of vectors.
Fix the shift amount when unrolling a vector shift into scalar shifts.
Fix problem in getShuffleScalarElt where it assumes that the input of
a bit convert must be a vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60740 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 36 | ||||
-rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 6 |
2 files changed, 33 insertions, 9 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index d61d6ca..445d32f 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -297,6 +297,9 @@ private: SDValue ExpandEXTRACT_SUBVECTOR(SDValue Op); SDValue ExpandEXTRACT_VECTOR_ELT(SDValue Op); + + // Returns the legalized (truncated or extended) shift amount. + SDValue LegalizeShiftAmount(SDValue ShiftAmt); }; } @@ -786,8 +789,19 @@ SDValue SelectionDAGLegalize::UnrollVectorOp(SDValue Op) { Operands[j] = Operand; } } - Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT, - &Operands[0], Operands.size())); + + switch (Op.getOpcode()) { + default: + Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT, + &Operands[0], Operands.size())); + break; + case ISD::SHL: + case ISD::SRA: + case ISD::SRL: + Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT, Operands[0], + LegalizeShiftAmount(Operands[1]))); + break; + } } return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size()); @@ -850,6 +864,17 @@ PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx) { PseudoSourceValue::getFixedStack(SPFI), 0); } +SDValue SelectionDAGLegalize::LegalizeShiftAmount(SDValue ShiftAmt) { + if (TLI.getShiftAmountTy().bitsLT(ShiftAmt.getValueType())) + return DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), ShiftAmt); + + if (TLI.getShiftAmountTy().bitsGT(ShiftAmt.getValueType())) + return DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), ShiftAmt); + + return ShiftAmt; +} + + /// LegalizeOp - We know that the specified value has a legal type, and /// that its operands are legal. Now ensure that the operation itself /// is legal, recursively ensuring that the operands' operations remain @@ -3094,11 +3119,8 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { Node->getOpcode() == ISD::SRL || Node->getOpcode() == ISD::SRA) && !Node->getValueType(0).isVector()) { - if (TLI.getShiftAmountTy().bitsLT(Tmp2.getValueType())) - Tmp2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Tmp2); - else if (TLI.getShiftAmountTy().bitsGT(Tmp2.getValueType())) - Tmp2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Tmp2); - } + Tmp2 = LegalizeShiftAmount(Tmp2); + } Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 6fc2a67..34f0cca 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -2066,7 +2066,8 @@ SDValue SelectionDAG::getShuffleScalarElt(const SDNode *N, unsigned i) { if (V.getOpcode() == ISD::BIT_CONVERT) { V = V.getOperand(0); - if (V.getValueType().getVectorNumElements() != NumElems) + MVT VVT = V.getValueType(); + if (!VVT.isVector() || VVT.getVectorNumElements() != NumElems) return SDValue(); } if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) @@ -2418,7 +2419,8 @@ SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, "Shift operators return type must be the same as their first arg"); assert(VT.isInteger() && N2.getValueType().isInteger() && "Shifts only work on integers"); - assert(N2.getValueType() == TLI.getShiftAmountTy() && + assert((N2.getValueType() == TLI.getShiftAmountTy() || + (N2.getValueType().isVector() && N2.getValueType().isInteger())) && "Wrong type for shift amount"); // Always fold shifts of i1 values so the code generator doesn't need to |