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| author | Owen Anderson <resistor@mac.com> | 2010-11-30 18:38:28 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2010-11-30 18:38:28 +0000 |
| commit | eb05a8d250fb4da51279efc59e99a54eaf5b60ed (patch) | |
| tree | ee9e4dc09ce4efd4fe42a7b0879c57afd4242edb /lib | |
| parent | a0d2c8a40f890345237abfa9cece16c517e1e280 (diff) | |
| download | external_llvm-eb05a8d250fb4da51279efc59e99a54eaf5b60ed.zip external_llvm-eb05a8d250fb4da51279efc59e99a54eaf5b60ed.tar.gz external_llvm-eb05a8d250fb4da51279efc59e99a54eaf5b60ed.tar.bz2 | |
Provide encodings for a few more load/store variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120439 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/ARM/ARMInstrThumb2.td | 20 |
1 files changed, 16 insertions, 4 deletions
diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index 1f8e9fb..8bee600 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -1396,8 +1396,8 @@ def t2LDRSH_POST : T2Iidxld<1, 0b01, 0, (outs GPR:$dst, GPR:$Rn), // for disassembly only. // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4 class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii> - : T2Ii8<(outs GPR:$dst), (ins t2addrmode_imm8:$addr), ii, opc, - "\t$dst, $addr", []> { + : T2Ii8<(outs GPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc, + "\t$Rt, $addr", []> { let Inst{31-27} = 0b11111; let Inst{26-25} = 0b00; let Inst{24} = signed; @@ -1406,6 +1406,12 @@ class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii> let Inst{20} = 1; // load let Inst{11} = 1; let Inst{10-8} = 0b110; // PUW. + + bits<4> Rt; + bits<13> addr; + let Inst{15-12} = Rt{3-0}; + let Inst{19-16} = addr{12-9}; + let Inst{7-0} = addr{7-0}; } def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>; @@ -1476,8 +1482,8 @@ def t2STRB_POST : T2Iidxst<0, 0b00, 0, (outs GPR:$base_wb), // only. // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4 class T2IstT<bits<2> type, string opc, InstrItinClass ii> - : T2Ii8<(outs GPR:$src), (ins t2addrmode_imm8:$addr), ii, opc, - "\t$src, $addr", []> { + : T2Ii8<(outs GPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc, + "\t$Rt, $addr", []> { let Inst{31-27} = 0b11111; let Inst{26-25} = 0b00; let Inst{24} = 0; // not signed @@ -1486,6 +1492,12 @@ class T2IstT<bits<2> type, string opc, InstrItinClass ii> let Inst{20} = 0; // store let Inst{11} = 1; let Inst{10-8} = 0b110; // PUW + + bits<4> Rt; + bits<13> addr; + let Inst{15-12} = Rt{3-0}; + let Inst{19-16} = addr{12-9}; + let Inst{7-0} = addr{7-0}; } def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>; |