diff options
author | Scott Michel <scottm@aero.org> | 2009-01-05 01:34:35 +0000 |
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committer | Scott Michel <scottm@aero.org> | 2009-01-05 01:34:35 +0000 |
commit | ed741dde287b566920fb54b47810824038de55cf (patch) | |
tree | c838de2a939297850d415372665955d60f3864b2 /lib | |
parent | 6cd0c048b88b96f90d0dd126995f014527c36a3d (diff) | |
download | external_llvm-ed741dde287b566920fb54b47810824038de55cf.zip external_llvm-ed741dde287b566920fb54b47810824038de55cf.tar.gz external_llvm-ed741dde287b566920fb54b47810824038de55cf.tar.bz2 |
CellSPU:
- Fix (brcond (setq ...)) bug, where BRNZ should have been used vice BRZ.
- Kill unused/unnecessary nodes in SPUNodes.td
- Beef out the i64operations.c test harness to use a lot of unaligned
loads, test loops and LLVM loop/basic block optimizations; run the
test harness successfully on real Cell hardware.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61664 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/Target/CellSPU/SPU64InstrInfo.td | 65 | ||||
-rw-r--r-- | lib/Target/CellSPU/SPUInstrInfo.td | 42 | ||||
-rw-r--r-- | lib/Target/CellSPU/SPUNodes.td | 10 |
3 files changed, 82 insertions, 35 deletions
diff --git a/lib/Target/CellSPU/SPU64InstrInfo.td b/lib/Target/CellSPU/SPU64InstrInfo.td index 4159133..f7a2fd0 100644 --- a/lib/Target/CellSPU/SPU64InstrInfo.td +++ b/lib/Target/CellSPU/SPU64InstrInfo.td @@ -22,6 +22,9 @@ // 4. v2i64 setcc results are v4i32, which can be converted to a FSM mask (TODO) // [Note: this may be moot, since gb produces v4i32 or r32.] // +// 5. The code sequences for r64 and v2i64 are probably overly conservative, +// compared to the code that gcc produces. +// // M00$E B!tes Kan be Pretty N@sTi!!!!! (appologies to Monty!) //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ @@ -41,18 +44,23 @@ class I64SETCCNegCond<PatFrag cond, CodeFrag compare>: Pat<(cond R64C:$rA, R64C:$rB), (XORIr32 compare.Fragment, -1)>; +// The generic i64 select pattern, which assumes that the comparison result +// is in a 32-bit register that contains a select mask pattern (i.e., gather +// bits result): + +def : Pat<(select R32C:$rC, R64C:$rB, R64C:$rA), + (SELBr64_cond R64C:$rA, R64C:$rB, (FSMr32 R32C:$rC))>; + +//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ // The i64 seteq fragment that does the scalar->vector conversion and // comparison: def CEQr64compare: CodeFrag<(CGTIv4i32 (GBv4i32 (CEQv4i32 (ORv2i64_i64 R64C:$rA), - (ORv2i64_i64 R64C:$rB))), - 0x0000000c)>; - + (ORv2i64_i64 R64C:$rB))), 0xb)>; // The i64 seteq fragment that does the vector comparison def CEQv2i64compare: - CodeFrag<(CGTIv4i32 (GBv4i32 (CEQv4i32 VECREG:$rA, VECREG:$rB)), - 0x0000000f)>; + CodeFrag<(CEQIv4i32 (GBv4i32 (CEQv4i32 VECREG:$rA, VECREG:$rB)), 0xf)>; // i64 seteq (equality): the setcc result is i32, which is converted to a // vector FSM mask when used in a select pattern. @@ -73,11 +81,52 @@ defm I64EQ: CompareEqual64; def : Pat<(seteq R64C:$rA, R64C:$rB), I64EQr64.Fragment>; def : Pat<(seteq (v2i64 VECREG:$rA), (v2i64 VECREG:$rB)), I64EQv2i64.Fragment>; -def : Pat<(select R32C:$rC, R64C:$rB, R64C:$rA), - (SELBr64_cond R64C:$rA, R64C:$rB, (FSMr32 R32C:$rC))>; - // i64 setne: def : I64SETCCNegCond<setne, I64EQr64>; def : I64SELECTNegCond<setne, I64EQr64>; +//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ // i64 setugt: +//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ + +def CLGTr64ugt: + CodeFrag<(CLGTv4i32 (ORv2i64_i64 R64C:$rA), (ORv2i64_i64 R64C:$rB))>; + +def CLGTr64eq: + CodeFrag<(CEQv4i32 (ORv2i64_i64 R64C:$rA), (ORv2i64_i64 R64C:$rB))>; + +def CLGTr64compare: + CodeFrag<(SELBv2i64 CLGTr64ugt.Fragment, + (XSWDv2i64 CLGTr64ugt.Fragment), + CLGTr64eq.Fragment)>; + +def CLGTv2i64ugt: + CodeFrag<(CLGTv4i32 VECREG:$rA, VECREG:$rB)>; + +def CLGTv2i64eq: + CodeFrag<(CEQv4i32 VECREG:$rA, VECREG:$rB)>; + +def CLGTv2i64compare: + CodeFrag<(SELBv2i64 CLGTv2i64ugt.Fragment, + (XSWDv2i64 CLGTr64ugt.Fragment), + CLGTv2i64eq.Fragment)>; + +multiclass CompareLogicalGreaterThan64 { + // Plain old comparison, converts back to i32 scalar + def r64: CodeFrag<(ORi32_v4i32 CLGTr64compare.Fragment)>; + def v2i64: CodeFrag<CLGTv2i64compare.Fragment>; + + // SELB mask from FSM: + def r64mask: CodeFrag<(ORi32_v4i32 (FSMv4i32 CLGTr64compare.Fragment))>; + def v2i64mask: CodeFrag<(ORi32_v4i32 (FSMv4i32 CLGTv2i64compare.Fragment))>; +} + +defm I64LGT: CompareLogicalGreaterThan64; + +def : Pat<(setugt R64C:$rA, R64C:$rB), I64LGTr64.Fragment>; +def : Pat<(setugt (v2i64 VECREG:$rA), (v2i64 VECREG:$rB)), + I64LGTv2i64.Fragment>; + +// i64 setult: +def : I64SETCCNegCond<setule, I64LGTr64>; +def : I64SELECTNegCond<setule, I64LGTr64>; diff --git a/lib/Target/CellSPU/SPUInstrInfo.td b/lib/Target/CellSPU/SPUInstrInfo.td index 751f36e..1ceaf1a 100644 --- a/lib/Target/CellSPU/SPUInstrInfo.td +++ b/lib/Target/CellSPU/SPUInstrInfo.td @@ -1176,23 +1176,31 @@ def XSHWr16: "xshw\t$rDst, $rSrc", IntegerOp, [(set R32C:$rDst, (sext R16C:$rSrc))]>; -def XSWDvec: - RRForm_1<0b01100101010, (outs VECREG:$rDst), (ins VECREG:$rSrc), - "xswd\t$rDst, $rSrc", IntegerOp, - [(set (v2i64 VECREG:$rDst), (sext (v4i32 VECREG:$rSrc)))]>; - -def XSWDr64: - RRForm_1<0b01100101010, (outs R64C:$rDst), (ins R64C:$rSrc), - "xswd\t$rDst, $rSrc", IntegerOp, - [(set R64C:$rDst, (sext_inreg R64C:$rSrc, i32))]>; +// Sign-extend words to doublewords (32->64 bits) -def XSWDr32: - RRForm_1<0b01100101010, (outs R64C:$rDst), (ins R32C:$rSrc), +class XSWDInst<dag OOL, dag IOL, list<dag> pattern>: + RRForm_1<0b01100101010, OOL, IOL, "xswd\t$rDst, $rSrc", IntegerOp, - [(set R64C:$rDst, (SPUsext32_to_64 R32C:$rSrc))]>; + pattern>; + +class XSWDVecInst<ValueType in_vectype, ValueType out_vectype>: + XSWDInst<(outs VECREG:$rDst), (ins VECREG:$rSrc), + [(set (out_vectype VECREG:$rDst), + (sext (out_vectype VECREG:$rSrc)))]>; + +class XSWDRegInst<RegisterClass in_rclass, RegisterClass out_rclass>: + XSWDInst<(outs out_rclass:$rDst), (ins in_rclass:$rSrc), + [(set out_rclass:$rDst, (sext in_rclass:$rSrc))]>; + +multiclass ExtendWordToDoubleWord { + def v2i64: XSWDVecInst<v4i32, v2i64>; + def r64: XSWDRegInst<R32C, R64C>; + + def r64_inreg: XSWDInst<(outs R64C:$rDst), (ins R64C:$rSrc), + [(set R64C:$rDst, (sext_inreg R64C:$rSrc, i32))]>; +} -def : Pat<(sext R32C:$inp), - (XSWDr32 R32C:$inp)>; +defm XSWD : ExtendWordToDoubleWord; // AND operations @@ -3511,7 +3519,7 @@ let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 in { def BI: BIForm<0b00010101100, "bi\t$func", [(brind R32C:$func)]>; - // Various branches: + // Conditional branches: class BRNZInst<dag IOL, list<dag> pattern>: RI16Form<0b010000100, (outs), IOL, "brnz\t$rCond,$dest", BranchResolv, pattern>; @@ -3651,8 +3659,8 @@ multiclass BranchCondEQ<PatFrag cond, SPUInstr brinst16, SPUInstr brinst32> (brinst32 (CEQr32 R32C:$rA, R32C:$rB), bb:$dest)>; } -defm BRCONDeq : BranchCondEQ<seteq, BRHZr16, BRZr32>; -defm BRCONDne : BranchCondEQ<setne, BRHNZr16, BRNZr32>; +defm BRCONDeq : BranchCondEQ<seteq, BRHNZr16, BRNZr32>; +defm BRCONDne : BranchCondEQ<setne, BRHZr16, BRZr32>; multiclass BranchCondLGT<PatFrag cond, SPUInstr brinst16, SPUInstr brinst32> { diff --git a/lib/Target/CellSPU/SPUNodes.td b/lib/Target/CellSPU/SPUNodes.td index 89a52ee..0725d72 100644 --- a/lib/Target/CellSPU/SPUNodes.td +++ b/lib/Target/CellSPU/SPUNodes.td @@ -137,16 +137,6 @@ def SPUaform : SDNode<"SPUISD::AFormAddr", SDTIntBinOp, []>; // Indirect [D-Form "imm($reg)" and X-Form "$reg($reg)"] addresses def SPUindirect : SDNode<"SPUISD::IndirectAddr", SDTIntBinOp, []>; -// SPU 32-bit sign-extension to 64-bits -def SPUsext32_to_64: SDNode<"SPUISD::SEXT32TO64", SDTIntExtendOp, []>; - -// Branches: - -def SPUbrnz : SDNode<"SPUISD::BR_NOTZERO", SDTBrcond, [SDNPHasChain]>; -def SPUbrz : SDNode<"SPUISD::BR_ZERO", SDTBrcond, [SDNPHasChain]>; -/* def SPUbinz : SDNode<"SPUISD::BR_NOTZERO", SDTBrind, [SDNPHasChain]>; -def SPUbiz : SDNode<"SPUISD::BR_ZERO", SPUBrind, [SDNPHasChain]>; */ - //===----------------------------------------------------------------------===// // Constraints: (taken from PPCInstrInfo.td) //===----------------------------------------------------------------------===// |