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| author | Owen Anderson <resistor@mac.com> | 2011-04-06 22:45:55 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2011-04-06 22:45:55 +0000 |
| commit | ef7fb17936ef38153e0a8c8146229d618722eb15 (patch) | |
| tree | b1bcd2d5d0a47fd06084924a4656de9ac25e21bc /lib | |
| parent | d418194036e9e05f47154535ddb9f1f1c8bc592b (diff) | |
| download | external_llvm-ef7fb17936ef38153e0a8c8146229d618722eb15.zip external_llvm-ef7fb17936ef38153e0a8c8146229d618722eb15.tar.gz external_llvm-ef7fb17936ef38153e0a8c8146229d618722eb15.tar.bz2 | |
Cleanups from Jim: remove redundant constraints and a dead FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129036 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 16 |
1 files changed, 5 insertions, 11 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 3735293..b787d35 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -940,16 +940,13 @@ let usesCustomInserter = 1 in { multiclass AI1_adde_sube_s_irs<PatFrag opnode, bit Commutable = 0> { def Sri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), Size4Bytes, IIC_iALUi, - [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>, - Requires<[IsARM]>; + [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>; def Srr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), Size4Bytes, IIC_iALUr, - [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>, - Requires<[IsARM]>; + [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>; def Srs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), Size4Bytes, IIC_iALUsr, - [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>, - Requires<[IsARM]>; + [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>; } } } @@ -2298,17 +2295,14 @@ def RSCrs : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), } } -// FIXME: Allow these to be predicated. // NOTE: CPSR def omitted because it will be handled by the custom inserter. let usesCustomInserter = 1, Uses = [CPSR] in { def RSCSri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), Size4Bytes, IIC_iALUi, - [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>, - Requires<[IsARM]>; + [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>; def RSCSrs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), Size4Bytes, IIC_iALUsr, - [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>, - Requires<[IsARM]>; + [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>; } // (sub X, imm) gets canonicalized to (add X, -imm). Match this form. |