diff options
| author | Evan Cheng <evan.cheng@apple.com> | 2010-10-01 21:40:30 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2010-10-01 21:40:30 +0000 |
| commit | f2e515d314d3651199a4f90d5ce39e52fd79fa40 (patch) | |
| tree | b8b81009b617eae4e6ee476673b420520df2a774 /lib | |
| parent | 2e11b558e934c89148ebc2462f1c624187afd6af (diff) | |
| download | external_llvm-f2e515d314d3651199a4f90d5ce39e52fd79fa40.zip external_llvm-f2e515d314d3651199a4f90d5ce39e52fd79fa40.tar.gz external_llvm-f2e515d314d3651199a4f90d5ce39e52fd79fa40.tar.bz2 | |
Add operand cycles for vldr / vstr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115353 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/ARM/ARMScheduleA8.td | 12 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMScheduleA9.td | 13 |
2 files changed, 17 insertions, 8 deletions
diff --git a/lib/Target/ARM/ARMScheduleA8.td b/lib/Target/ARM/ARMScheduleA8.td index d2e1df1..ef93e1d 100644 --- a/lib/Target/ARM/ARMScheduleA8.td +++ b/lib/Target/ARM/ARMScheduleA8.td @@ -384,7 +384,8 @@ def CortexA8Itineraries : ProcessorItineraries< InstrItinData<IIC_fpLoad32, [InstrStage<1, [A8_Issue], 0>, InstrStage<1, [A8_Pipe0, A8_Pipe1]>, InstrStage<1, [A8_LdSt0], 0>, - InstrStage<1, [A8_NLSPipe]>]>, + InstrStage<1, [A8_NLSPipe]>], + [2, 1]>, // // Double-precision FP Load // use A8_Issue to enforce the 1 load/store per cycle limit @@ -393,7 +394,8 @@ def CortexA8Itineraries : ProcessorItineraries< InstrStage<1, [A8_Pipe1]>, InstrStage<1, [A8_Pipe0, A8_Pipe1]>, InstrStage<1, [A8_LdSt0], 0>, - InstrStage<1, [A8_NLSPipe]>]>, + InstrStage<1, [A8_NLSPipe]>], + [2, 1]>, // // FP Load Multiple // use A8_Issue to enforce the 1 load/store per cycle limit @@ -409,7 +411,8 @@ def CortexA8Itineraries : ProcessorItineraries< InstrItinData<IIC_fpStore32,[InstrStage<1, [A8_Issue], 0>, InstrStage<1, [A8_Pipe0, A8_Pipe1]>, InstrStage<1, [A8_LdSt0], 0>, - InstrStage<1, [A8_NLSPipe]>]>, + InstrStage<1, [A8_NLSPipe]>], + [1, 1]>, // // Double-precision FP Store // use A8_Issue to enforce the 1 load/store per cycle limit @@ -418,7 +421,8 @@ def CortexA8Itineraries : ProcessorItineraries< InstrStage<1, [A8_Pipe1]>, InstrStage<1, [A8_Pipe0, A8_Pipe1]>, InstrStage<1, [A8_LdSt0], 0>, - InstrStage<1, [A8_NLSPipe]>]>, + InstrStage<1, [A8_NLSPipe]>], + [1, 1]>, // // FP Store Multiple // use A8_Issue to enforce the 1 load/store per cycle limit diff --git a/lib/Target/ARM/ARMScheduleA9.td b/lib/Target/ARM/ARMScheduleA9.td index 8acc172..729c962 100644 --- a/lib/Target/ARM/ARMScheduleA9.td +++ b/lib/Target/ARM/ARMScheduleA9.td @@ -482,13 +482,16 @@ def CortexA9Itineraries : ProcessorItineraries< InstrItinData<IIC_fpLoad32, [InstrStage<1, [A9_DRegsVFP], 0, Required>, InstrStage<2, [A9_DRegsN], 0, Reserved>, InstrStage<1, [A9_Pipe1], 0>, - InstrStage<1, [A9_MUX0, A9_NPipe]>]>, + InstrStage<1, [A9_MUX0, A9_NPipe]>], + [1, 1]>, // // Double-precision FP Load + // FIXME: Result latency is 1 if address is 64-bit aligned. InstrItinData<IIC_fpLoad64, [InstrStage<1, [A9_DRegsVFP], 0, Required>, InstrStage<2, [A9_DRegsN], 0, Reserved>, InstrStage<1, [A9_Pipe1], 0>, - InstrStage<1, [A9_MUX0, A9_NPipe]>]>, + InstrStage<1, [A9_MUX0, A9_NPipe]>], + [2, 1]>, // // FP Load Multiple InstrItinData<IIC_fpLoadm, [InstrStage<1, [A9_DRegsVFP], 0, Required>, @@ -500,13 +503,15 @@ def CortexA9Itineraries : ProcessorItineraries< InstrItinData<IIC_fpStore32,[InstrStage<1, [A9_DRegsVFP], 0, Required>, InstrStage<2, [A9_DRegsN], 0, Reserved>, InstrStage<1, [A9_Pipe1], 0>, - InstrStage<1, [A9_MUX0, A9_NPipe]>]>, + InstrStage<1, [A9_MUX0, A9_NPipe]>], + [1, 1]>, // // Double-precision FP Store InstrItinData<IIC_fpStore64,[InstrStage<1, [A9_DRegsVFP], 0, Required>, InstrStage<2, [A9_DRegsN], 0, Reserved>, InstrStage<1, [A9_Pipe1], 0>, - InstrStage<1, [A9_MUX0, A9_NPipe]>]>, + InstrStage<1, [A9_MUX0, A9_NPipe]>], + [1, 1]>, // // FP Store Multiple InstrItinData<IIC_fpStorem, [InstrStage<1, [A9_DRegsVFP], 0, Required>, |