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authorHal Finkel <hfinkel@anl.gov>2012-08-06 21:21:44 +0000
committerHal Finkel <hfinkel@anl.gov>2012-08-06 21:21:44 +0000
commitf45717e985260e9416dbd2fe8df471d48705c86a (patch)
tree923d6a32b94723bad2265bccd735fbea08895d62 /lib
parentb0f6759ab93b42570d71665b13d24ca2c4a5f276 (diff)
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MFTB on PPC64 should really be encoded using MFSPR.
The MFTB instruction itself is being phased out, and its functionality is provided by MFSPR. According to the ISA docs, using MFSPR works on all known chips except for the 601 (which did not have a timebase register anyway) and the POWER3. Thanks to Adhemerval Zanella for pointing this out! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161346 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r--lib/Target/PowerPC/PPCInstr64Bit.td4
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/PowerPC/PPCInstr64Bit.td b/lib/Target/PowerPC/PPCInstr64Bit.td
index 92a5051..5df735a 100644
--- a/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -266,8 +266,8 @@ def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins G8RC:$rS),
}
let Pattern = [(set G8RC:$rT, readcyclecounter)] in
-def MFTB8 : XFXForm_1_ext<31, 371, 268, (outs G8RC:$rT), (ins),
- "mftb $rT", SprMFTB>,
+def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs G8RC:$rT), (ins),
+ "mfspr $rT, 268", SprMFTB>,
PPC970_DGroup_First, PPC970_Unit_FXU;
let Defs = [X1], Uses = [X1] in