Refactor aliased packed logical instructions, also add

AVX AND,OR,XOR,NAND{P}{S,D}{rr,rm} instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106374 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 26 insertions, 39 deletions

diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td
index 90c3fd8..e0a550b 100644
--- a/lib/Target/X86/X86InstrSSE.td
+++ b/lib/Target/X86/X86InstrSSE.td
@@ -404,13 +404,14 @@ multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
                            RegisterClass RC, ValueType vt,
                            X86MemOperand x86memop, PatFrag mem_frag,
-                           Domain d> {
+                           Domain d, bit MayLoad = 0> {
   let isCommutable = 1 in
     def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
                 OpcodeStr, [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))],d>;
-  def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
-              OpcodeStr, [(set RC:$dst, (OpNode RC:$src1,
-                                                (mem_frag addr:$src2)))],d>;
+  let mayLoad = MayLoad in
+    def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
+                OpcodeStr, [(set RC:$dst, (OpNode RC:$src1,
+                                                  (mem_frag addr:$src2)))],d>;
 }
 
 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
@@ -666,50 +667,36 @@ def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
 ///
 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
-                                       SDNode OpNode, int NoPat = 0,
-                                       bit MayLoad = 0, bit Commutable = 1> {
-  def PSrr : PSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
-                      !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
-                      !if(NoPat, []<dag>,
-                          [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))])> {
-    let isCommutable = Commutable;
-  }
+                                       SDNode OpNode, bit MayLoad = 0> {
+  let isAsmParserOnly = 1 in {
+    defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
+                "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode, FR32,
+                f32, f128mem, memopfsf32, SSEPackedSingle, MayLoad>, VEX_4V;
 
-  def PDrr : PDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
-                      !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
-                      !if(NoPat, []<dag>,
-                          [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))])> {
-    let isCommutable = Commutable;
+    defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
+                "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode, FR64,
+                f64, f128mem, memopfsf64, SSEPackedDouble, MayLoad>, OpSize,
+                VEX_4V;
   }
 
-  def PSrm : PSI<opc, MRMSrcMem, (outs FR32:$dst),
-                      (ins FR32:$src1, f128mem:$src2),
-                      !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
-                      !if(NoPat, []<dag>,
-                          [(set FR32:$dst, (OpNode FR32:$src1,
-                                               (memopfsf32 addr:$src2)))])> {
-    let mayLoad = MayLoad;
-  }
+  let Constraints = "$src1 = $dst" in {
+    defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
+                "ps\t{$src2, $dst|$dst, $src2}"), OpNode, FR32, f32,
+                f128mem, memopfsf32, SSEPackedSingle, MayLoad>, TB;
 
-  def PDrm : PDI<opc, MRMSrcMem, (outs FR64:$dst),
-                      (ins FR64:$src1, f128mem:$src2),
-                      !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
-                      !if(NoPat, []<dag>,
-                          [(set FR64:$dst, (OpNode FR64:$src1,
-                                               (memopfsf64 addr:$src2)))])> {
-    let mayLoad = MayLoad;
+    defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
+                "pd\t{$src2, $dst|$dst, $src2}"), OpNode, FR64, f64,
+                f128mem, memopfsf64, SSEPackedDouble, MayLoad>, TB, OpSize;
   }
 }
 
 // Alias bitwise logical operations using SSE logical ops on packed FP values.
-let Constraints = "$src1 = $dst" in {
-  defm FsAND  : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
-  defm FsOR   : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
-  defm FsXOR  : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
+defm FsAND  : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
+defm FsOR   : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
+defm FsXOR  : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
 
-  let neverHasSideEffects = 1 in
-    defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef, 1, 1, 0>;
-}
+let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
+  defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef, 1>;
 
 /// basic_sse12_fp_binop_rm - SSE 1 & 2 binops come in both scalar and
 /// vector forms.