Checkin changes to:

1. Clean up the TargetMachine structure.  No more wierd pointers that have to
   be cast around and taken care of by the target.
2. Instruction Scheduling now takes the schedinfo as an argument.  The same
   should be done with the instinfo, it just isn't now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@565 91177308-0d34-0410-b5e6-96231b3b80d8

4 files changed, 55 insertions, 28 deletions

diff --git a/lib/CodeGen/InstrSched/InstrScheduling.cpp b/lib/CodeGen/InstrSched/InstrScheduling.cpp
index 825e454..2358687 100644
--- a/lib/CodeGen/InstrSched/InstrScheduling.cpp
+++ b/lib/CodeGen/InstrSched/InstrScheduling.cpp
@@ -401,6 +401,7 @@ private:
   
 public:
   /*ctor*/	SchedulingManager	(const TargetMachine& _target,
+					 const MachineSchedInfo &schedinfo, 
 					 const SchedGraph* graph,
 					 SchedPriorities& schedPrio);
   /*dtor*/	~SchedulingManager	() {}
@@ -562,16 +563,17 @@ private:
 
 /*ctor*/
 SchedulingManager::SchedulingManager(const TargetMachine& target,
+				     const MachineSchedInfo &schedinfo,
 				     const SchedGraph* graph,
 				     SchedPriorities& _schedPrio)
-  : nslots(target.getSchedInfo().getMaxNumIssueTotal()),
-    schedInfo(target.getSchedInfo()),
+  : nslots(schedinfo.getMaxNumIssueTotal()),
+    schedInfo(schedinfo),
     schedPrio(_schedPrio),
     isched(nslots, graph->getNumNodes()),
     totalInstrCount(graph->getNumNodes() - 2),
     nextEarliestIssueTime(0),
     choicesForSlot(nslots),
-    numInClass(target.getSchedInfo().getNumSchedClasses(), 0),	// set all to 0
+    numInClass(schedinfo.getNumSchedClasses(), 0),	// set all to 0
     nextEarliestStartTime(target.getInstrInfo().getNumRealOpCodes(),
 			  (cycles_t) 0)				// set all to 0
 {
@@ -623,10 +625,8 @@ SchedulingManager::updateEarliestStartTimes(const SchedGraphNode* node,
 //   are still in SSA form.
 //---------------------------------------------------------------------------
 
-bool
-ScheduleInstructionsWithSSA(Method* method,
-			    const TargetMachine &target)
-{
+bool ScheduleInstructionsWithSSA(Method* method, const TargetMachine &target,
+				 const MachineSchedInfo &schedInfo) {
   SchedGraphSet graphSet(method, target);	
   
   if (SchedDebugLevel >= Sched_PrintSchedGraphs)
@@ -648,7 +648,7 @@ ScheduleInstructionsWithSSA(Method* method,
 	cout << endl << "*** TRACE OF INSTRUCTION SCHEDULING OPERATIONS\n\n";
       
       SchedPriorities schedPrio(method, graph);	     // expensive!
-      SchedulingManager S(target, graph, schedPrio);
+      SchedulingManager S(target, schedInfo, graph, schedPrio);
       
       ChooseInstructionsForDelaySlots(S, bb, graph); // modifies graph
       
diff --git a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
index 825e454..2358687 100644
--- a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
+++ b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
@@ -401,6 +401,7 @@ private:
   
 public:
   /*ctor*/	SchedulingManager	(const TargetMachine& _target,
+					 const MachineSchedInfo &schedinfo, 
 					 const SchedGraph* graph,
 					 SchedPriorities& schedPrio);
   /*dtor*/	~SchedulingManager	() {}
@@ -562,16 +563,17 @@ private:
 
 /*ctor*/
 SchedulingManager::SchedulingManager(const TargetMachine& target,
+				     const MachineSchedInfo &schedinfo,
 				     const SchedGraph* graph,
 				     SchedPriorities& _schedPrio)
-  : nslots(target.getSchedInfo().getMaxNumIssueTotal()),
-    schedInfo(target.getSchedInfo()),
+  : nslots(schedinfo.getMaxNumIssueTotal()),
+    schedInfo(schedinfo),
     schedPrio(_schedPrio),
     isched(nslots, graph->getNumNodes()),
     totalInstrCount(graph->getNumNodes() - 2),
     nextEarliestIssueTime(0),
     choicesForSlot(nslots),
-    numInClass(target.getSchedInfo().getNumSchedClasses(), 0),	// set all to 0
+    numInClass(schedinfo.getNumSchedClasses(), 0),	// set all to 0
     nextEarliestStartTime(target.getInstrInfo().getNumRealOpCodes(),
 			  (cycles_t) 0)				// set all to 0
 {
@@ -623,10 +625,8 @@ SchedulingManager::updateEarliestStartTimes(const SchedGraphNode* node,
 //   are still in SSA form.
 //---------------------------------------------------------------------------
 
-bool
-ScheduleInstructionsWithSSA(Method* method,
-			    const TargetMachine &target)
-{
+bool ScheduleInstructionsWithSSA(Method* method, const TargetMachine &target,
+				 const MachineSchedInfo &schedInfo) {
   SchedGraphSet graphSet(method, target);	
   
   if (SchedDebugLevel >= Sched_PrintSchedGraphs)
@@ -648,7 +648,7 @@ ScheduleInstructionsWithSSA(Method* method,
 	cout << endl << "*** TRACE OF INSTRUCTION SCHEDULING OPERATIONS\n\n";
       
       SchedPriorities schedPrio(method, graph);	     // expensive!
-      SchedulingManager S(target, graph, schedPrio);
+      SchedulingManager S(target, schedInfo, graph, schedPrio);
       
       ChooseInstructionsForDelaySlots(S, bb, graph); // modifies graph
       
diff --git a/lib/Target/SparcV9/SparcV9Internals.h b/lib/Target/SparcV9/SparcV9Internals.h
index df290d6..606966d 100644
--- a/lib/Target/SparcV9/SparcV9Internals.h
+++ b/lib/Target/SparcV9/SparcV9Internals.h
@@ -8,12 +8,14 @@
 #ifndef SPARC_INTERNALS_H
 #define SPARC_INTERNALS_H
 
-#include "llvm/CodeGen/Sparc.h"
+#include "llvm/CodeGen/TargetMachine.h"
 #include "SparcRegInfo.h"
 
 #include <sys/types.h>
 #include "llvm/Type.h"
 
+class UltraSparc;
+
 // OpCodeMask definitions for the Sparc V9
 // 
 const OpCodeMask	Immed		= 0x00002000; // immed or reg operand?
@@ -1664,4 +1666,31 @@ protected:
   virtual void	initializeResources	();
 };
 
+
+//---------------------------------------------------------------------------
+// class UltraSparcMachine 
+// 
+// Purpose:
+//   Primary interface to machine description for the UltraSPARC.
+//   Primarily just initializes machine-dependent parameters in
+//   class TargetMachine, and creates machine-dependent subclasses
+//   for classes such as MachineInstrInfo. 
+//---------------------------------------------------------------------------
+
+class UltraSparc : public TargetMachine {
+  UltraSparcInstrInfo InstInfo;
+  UltraSparcSchedInfo InstSchedulingInfo;
+public:
+  UltraSparc();
+  virtual ~UltraSparc() {}
+
+  virtual const MachineInstrInfo& getInstrInfo() const { return InstInfo; }
+
+  // compileMethod - For the sparc, we do instruction selection, followed by
+  // delay slot scheduling, then register allocation.
+  //
+  virtual bool compileMethod(Method *M);
+};
+
+
 #endif
diff --git a/lib/Target/SparcV9/SparcV9TargetMachine.cpp b/lib/Target/SparcV9/SparcV9TargetMachine.cpp
index 80de2e7..cf09734 100644
--- a/lib/Target/SparcV9/SparcV9TargetMachine.cpp
+++ b/lib/Target/SparcV9/SparcV9TargetMachine.cpp
@@ -8,6 +8,7 @@
 //	7/15/01	 -  Vikram Adve  -  Created
 //**************************************************************************/
 
+#include "llvm/CodeGen/Sparc.h"
 #include "SparcInternals.h"
 #include "llvm/Method.h"
 #include "llvm/CodeGen/InstrScheduling.h"
@@ -91,22 +92,14 @@ UltraSparcSchedInfo::initializeResources()
 // 
 //---------------------------------------------------------------------------
 
-UltraSparc::UltraSparc() : TargetMachine("UltraSparc-Native") {
-  machineInstrInfo = new UltraSparcInstrInfo();
-  machineSchedInfo = new UltraSparcSchedInfo(machineInstrInfo); 
-  
+UltraSparc::UltraSparc() : TargetMachine("UltraSparc-Native"),
+			   InstSchedulingInfo(&InstInfo) {
   optSizeForSubWordData = 4;
   minMemOpWordSize = 8; 
   maxAtomicMemOpWordSize = 8;
   zeroRegNum = 0;			// %g0 always gives 0 on Sparc
 }
 
-UltraSparc::~UltraSparc() {
-  delete (UltraSparcInstrInfo*) machineInstrInfo;
-  delete (UltraSparcSchedInfo*) machineSchedInfo;
-}
-
-
 bool UltraSparc::compileMethod(Method *M) {
   if (SelectInstructionsForMethod(M, *this)) {
     cerr << "Instruction selection failed for method " << M->getName()
@@ -114,10 +107,15 @@ bool UltraSparc::compileMethod(Method *M) {
     return true;
   }
   
-  if (ScheduleInstructionsWithSSA(M, *this)) {
+  if (ScheduleInstructionsWithSSA(M, *this, InstSchedulingInfo)) {
     cerr << "Instruction scheduling before allocation failed for method "
        << M->getName() << "\n\n";
     return true;
   }
   return false;
 }
+
+// allocateSparcTargetMachine - Allocate and return a subclass of TargetMachine
+// that implements the Sparc backend.
+//
+TargetMachine *allocateSparcTargetMachine() { return new UltraSparc(); }