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author | Bill Wendling <isanbard@gmail.com> | 2011-10-12 23:03:40 +0000 |
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committer | Bill Wendling <isanbard@gmail.com> | 2011-10-12 23:03:40 +0000 |
commit | f6fb7ed53c786228445fc55e8d495ccead59b9ae (patch) | |
tree | f0df75224069055eb5cc43da328d1a97098a6f23 /lib | |
parent | 5c75af6eb72bd74bc35f46e5037dd5646e04f3b6 (diff) | |
download | external_llvm-f6fb7ed53c786228445fc55e8d495ccead59b9ae.zip external_llvm-f6fb7ed53c786228445fc55e8d495ccead59b9ae.tar.gz external_llvm-f6fb7ed53c786228445fc55e8d495ccead59b9ae.tar.bz2 |
We need to verify that the machine instruction we're using as a replacement for
our current machine instruction defines a register with the same register class
as what's being replaced. This showed up in the SPEC 403.gcc benchmark, where it
would ICE because a tail call was expecting one register class but was given
another. (The machine instruction verifier catches this situation.)
<rdar://problem/10270968>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141830 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/CodeGen/MachineCSE.cpp | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/lib/CodeGen/MachineCSE.cpp b/lib/CodeGen/MachineCSE.cpp index 3a60a37..7eda8c1 100644 --- a/lib/CodeGen/MachineCSE.cpp +++ b/lib/CodeGen/MachineCSE.cpp @@ -430,13 +430,24 @@ bool MachineCSE::ProcessBlock(MachineBasicBlock *MBB) { unsigned NewReg = CSMI->getOperand(i).getReg(); if (OldReg == NewReg) continue; + assert(TargetRegisterInfo::isVirtualRegister(OldReg) && TargetRegisterInfo::isVirtualRegister(NewReg) && "Do not CSE physical register defs!"); + if (!isProfitableToCSE(NewReg, OldReg, CSMI, MI)) { DoCSE = false; break; } + + // Don't perform CSE if the result of the old instruction cannot exist + // within the register class of the new instruction. + const TargetRegisterClass *OldRC = MRI->getRegClass(OldReg); + if (!MRI->constrainRegClass(NewReg, OldRC)) { + DoCSE = false; + break; + } + CSEPairs.push_back(std::make_pair(OldReg, NewReg)); --NumDefs; } |