Speed up the AllocationOrder class a bit.

Allow the central functions to be inlined, and use the argumentless
isHint() function when possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169319 91177308-0d34-0410-b5e6-96231b3b80d8

3 files changed, 19 insertions, 25 deletions

diff --git a/lib/CodeGen/AllocationOrder.cpp b/lib/CodeGen/AllocationOrder.cpp
index a767910..94754a0 100644
--- a/lib/CodeGen/AllocationOrder.cpp
+++ b/lib/CodeGen/AllocationOrder.cpp
@@ -35,6 +35,7 @@ AllocationOrder::AllocationOrder(unsigned VirtReg,
   const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo();
   Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
   TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM);
+  rewind();
 
   DEBUG({
     if (!Hints.empty()) {
@@ -45,21 +46,3 @@ AllocationOrder::AllocationOrder(unsigned VirtReg,
     }
   });
 }
-
-bool AllocationOrder::isHint(unsigned PhysReg) const {
-  return std::find(Hints.begin(), Hints.end(), PhysReg) != Hints.end();
-}
-
-unsigned AllocationOrder::next() {
-  if (Pos < Hints.size())
-    return Hints[Pos++];
-  ArrayRef<MCPhysReg>::iterator I = Order.begin() + (Pos - Hints.size());
-  ArrayRef<MCPhysReg>::iterator E = Order.end();
-  while (I != E) {
-    unsigned Reg = *I++;
-    ++Pos;
-    if (!isHint(Reg))
-      return Reg;
-  }
-  return 0;
-}
diff --git a/lib/CodeGen/AllocationOrder.h b/lib/CodeGen/AllocationOrder.h
index 9bcbc73..a5293f6 100644
--- a/lib/CodeGen/AllocationOrder.h
+++ b/lib/CodeGen/AllocationOrder.h
@@ -28,7 +28,7 @@ class VirtRegMap;
 class AllocationOrder {
   SmallVector<MCPhysReg, 16> Hints;
   ArrayRef<MCPhysReg> Order;
-  unsigned Pos;
+  int Pos;
 
 public:
   /// Create a new AllocationOrder for VirtReg.
@@ -42,16 +42,27 @@ public:
   /// Return the next physical register in the allocation order, or 0.
   /// It is safe to call next() again after it returned 0, it will keep
   /// returning 0 until rewind() is called.
-  unsigned next();
+  unsigned next() {
+    if (Pos < 0)
+      return Hints.end()[Pos++];
+    while (Pos < int(Order.size())) {
+      unsigned Reg = Order[Pos++];
+      if (!isHint(Reg))
+        return Reg;
+    }
+    return 0;
+  }
 
   /// Start over from the beginning.
-  void rewind() { Pos = 0; }
+  void rewind() { Pos = -int(Hints.size()); }
 
   /// Return true if the last register returned from next() was a preferred register.
-  bool isHint() const { return Pos <= Hints.size(); }
+  bool isHint() const { return Pos <= 0; }
 
   /// Return true if PhysReg is a preferred register.
-  bool isHint(unsigned PhysReg) const;
+  bool isHint(unsigned PhysReg) const {
+    return std::find(Hints.begin(), Hints.end(), PhysReg) != Hints.end();
+  }
 };
 
 } // end namespace llvm
diff --git a/lib/CodeGen/RegAllocGreedy.cpp b/lib/CodeGen/RegAllocGreedy.cpp
index 9942643..1884452 100644
--- a/lib/CodeGen/RegAllocGreedy.cpp
+++ b/lib/CodeGen/RegAllocGreedy.cpp
@@ -442,7 +442,7 @@ unsigned RAGreedy::tryAssign(LiveInterval &VirtReg,
   while ((PhysReg = Order.next()))
     if (!Matrix->checkInterference(VirtReg, PhysReg))
       break;
-  if (!PhysReg || Order.isHint(PhysReg))
+  if (!PhysReg || Order.isHint())
     return PhysReg;
 
   // PhysReg is available, but there may be a better choice.
@@ -661,7 +661,7 @@ unsigned RAGreedy::tryEvict(LiveInterval &VirtReg,
     BestPhys = PhysReg;
 
     // Stop if the hint can be used.
-    if (Order.isHint(PhysReg))
+    if (Order.isHint())
       break;
   }