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| author | Chris Lattner <sabre@nondot.org> | 2002-11-17 23:03:46 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2002-11-17 23:03:46 +0000 |
| commit | fb02a8b11f53958f2f2991053579df0254635cb5 (patch) | |
| tree | 9eb255c7038927081762bab2167c3898069362b6 /lib | |
| parent | ebdc7f32e9c2404d3a1cbe26bf65890cdc4d1f04 (diff) | |
| download | external_llvm-fb02a8b11f53958f2f2991053579df0254635cb5.zip external_llvm-fb02a8b11f53958f2f2991053579df0254635cb5.tar.gz external_llvm-fb02a8b11f53958f2f2991053579df0254635cb5.tar.bz2 | |
Rename registers to follow the intel style of all caps
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4731 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/X86/X86RegisterInfo.def | 56 |
1 files changed, 29 insertions, 27 deletions
diff --git a/lib/Target/X86/X86RegisterInfo.def b/lib/Target/X86/X86RegisterInfo.def index df75fa3..db03834 100644 --- a/lib/Target/X86/X86RegisterInfo.def +++ b/lib/Target/X86/X86RegisterInfo.def @@ -26,48 +26,50 @@ // is used as the destination register for instructions that do not produce a // value. Some frontends may use this as an operand register to mean special // things, for example, the Sparc backend uses R#0 to mean %g0 which always -// PRODUCES the value 0. The X86 backend does not use this value as an operand -// register. +// PRODUCES the value 0. +// +// The X86 backend uses this value as an operand register only in memory +// references where it means that there is no base or index register. // R(NoReg, "none", 0, 0) // 32 bit registers, ordered as the processor does... -R(EAX, "eax", MRF::INT32, 0) -R(ECX, "ecx", MRF::INT32, 0) -R(EDX, "edx", MRF::INT32, 0) -R(EBX, "ebx", MRF::INT32, 0) -R(ESP, "esp", MRF::INT32, 0) -R(EBP, "ebp", MRF::INT32, 0) -R(ESI, "esi", MRF::INT32, 0) -R(EDI, "edi", MRF::INT32, 0) +R(EAX, "EAX", MRF::INT32, 0) +R(ECX, "ECX", MRF::INT32, 0) +R(EDX, "EDX", MRF::INT32, 0) +R(EBX, "EBX", MRF::INT32, 0) +R(ESP, "ESP", MRF::INT32, 0) +R(EBP, "EBP", MRF::INT32, 0) +R(ESI, "ESI", MRF::INT32, 0) +R(EDI, "EDI", MRF::INT32, 0) // 16 bit registers, aliased with the corresponding 32 bit registers above -R(AX, "ax", MRF::INT16, 0) -R(CX, "cx", MRF::INT16, 0) -R(DX, "dx", MRF::INT16, 0) -R(BX, "bx", MRF::INT16, 0) -R(SP, "sp", MRF::INT16, 0) -R(BP, "bp", MRF::INT16, 0) -R(SI, "si", MRF::INT16, 0) -R(DI, "di", MRF::INT16, 0) +R(AX, "AX", MRF::INT16, 0) +R(CX, "CX", MRF::INT16, 0) +R(DX, "Dx", MRF::INT16, 0) +R(BX, "BX", MRF::INT16, 0) +R(SP, "SP", MRF::INT16, 0) +R(BP, "BP", MRF::INT16, 0) +R(SI, "SI", MRF::INT16, 0) +R(DI, "DI", MRF::INT16, 0) // 8 bit registers aliased with registers above as well -R(AL, "al", MRF::INT8, 0) -R(CL, "cl", MRF::INT8, 0) -R(DL, "dl", MRF::INT8, 0) -R(BL, "bl", MRF::INT8, 0) -R(AH, "ah", MRF::INT8, 0) -R(CH, "ch", MRF::INT8, 0) -R(DH, "dh", MRF::INT8, 0) -R(BH, "bh", MRF::INT8, 0) +R(AL, "AL", MRF::INT8, 0) +R(CL, "CL", MRF::INT8, 0) +R(DL, "DL", MRF::INT8, 0) +R(BL, "BL", MRF::INT8, 0) +R(AH, "AH", MRF::INT8, 0) +R(CH, "CH", MRF::INT8, 0) +R(DH, "DH", MRF::INT8, 0) +R(BH, "BH", MRF::INT8, 0) // Flags, Segment registers, etc... // This is a slimy hack to make it possible to say that flags are clobbered... // Ideally we'd model instructions based on which particular flag(s) they // could clobber. -R(EFLAGS, "eflags", MRF::INT8, 0) +R(EFLAGS, "EFLAGS", MRF::INT16, 0) // We are now done with the R macro #undef R |